A Complete Guide to SR Latch Implemented through NAND Gates

What is a Latch?

A latch is a level-sensitive, fundamental bistable memory circuit that stores one bit of data. Its state is transparently controlled by its input signals while the control (enable) signal is active.

What is an SR Latch?

An \(\mathsf{SR}\) (Set-Reset) Latch is the simplest bistable memory element, built from two cross-coupled gates. It has two inputs (\(\mathsf{S}\) and \(\mathsf{R}\)) and two complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)). It can be set to \(\mathsf{1}\), reset to \(\mathsf{0}\), or hold its previous state based on the input combinations.

What is an SR Latch based on NAND Gate?

A NAND-based \(\mathsf{SR}\) Latch is an implementation where the “hold” state occurs with both inputs (\(\mathsf{S}\) and \(\mathsf{R}\)) at logic ‘1’. The Set command is activated by a ‘0’ on \(\mathsf{S}\), and the Reset by a ‘0’ on \(\mathsf{R}\). The condition \(\mathsf{S=0, R=0}\) is forbidden as it leads to an invalid/undefined output state.

Evolution of an SR Latch

Basic SR Latch

A basic NAND SR latch is implemented using two cross-coupled NAND gates as shown in the figure. It has two inputs: \(\mathsf{S}\) and \(\mathsf{R}\), and two complementary outputs: \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\).

Based on the input combinations, the output could be in one of the following states:

Hence, when the output needs to remain unchanged, it is held in the hold state, when it is to be set or reset, the corresponding input is changed to 0 and the then returned to the hold state. Forbidden state inputs are never given to keep the latch performing in a predictable manner.

Analysis of a Basic NAND SR Latch

To understand the operational states of a NAND-based SR latch, we will apply a sequence of input combinations. The table above the latch diagram lists these specific (S, R) input values alongside their corresponding time intervals.

Below the circuit, the resulting output values illustrates how the \(\mathsf{Q}\)Q and \(\mathsf{\overline{Q}}\) values change in direct response to these inputs. By observing these timings, we can clearly trace the latch’s behavior through its set, reset, hold and forbidden states, providing a practical analysis of its core functionality.

While similar to timing diagrams, these tables focus exclusively on the steady-state values. They emphasize the final, logical result of each input combination, omitting the detailed signal transitions. The details are shown in the individual analysis of that timeframe.

Timestep \(\mathsf{t_0}\): Hold State

At time step \(\mathsf{}\)t₀, the figure depicts the latch’s initial state, with inputs \(\mathsf{S}\) and \(\mathsf{R}\) both held at logic \(\mathsf{1}\). This results in outputs \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\) at \(\mathsf{0}\) and \(\mathsf{1}\), respectively. Known as the hold state, this default input combination preserves the outputs without alteration from their previous values. The timing diagram, shown between the outputs, highlights the \(\mathsf{Q}\) output at \(\mathsf{t_0}\). The values at the inputs and outputs of the NAND gates show no change in the values during all of the \(\mathsf{t_0.}\)

Timestep \(\mathsf{t_1}\): Set State

At timestep \(\mathsf{t_1}\), the figure shows the initial values near the inputs and outputs of NAND gates \(\mathsf{n1}\) and \(\mathsf{n2}\), carried over from the end of the previous timestep. The first transition occurs when input \(\mathsf{S}\) drops from \(\mathsf{1}\) to \(\mathsf{0}\), marked by a star box to emphasize the analysis starting point. At this instant, \(\mathsf{\overline{Q}}\) remains at \(\mathsf{1}\), causing \(\mathsf{n1}\)’s output (\(\mathsf{Q}\)) to switch from \(\mathsf{0}\) to \(\mathsf{1}\). This new \(\mathsf{1}\) propagates to \(\mathsf{n2}\)’s input, where \(\mathsf{R}\) is still \(\mathsf{1}\), driving \(\mathsf{\overline{Q}}\) low to \(\mathsf{0}\). The resulting \(\mathsf{0}\) feeds back to \(\mathsf{n1}\), pairing with \(\mathsf{S=0}\) to lock \(\mathsf{Q}\) at \(\mathsf{1}\). Meanwhile, \(\mathsf{Q=1}\) and \(\mathsf{R=1}\) hold \(\mathsf{\overline{Q}}\) at \(\mathsf{0}\) as the circuit stabilizes. Thus, asserting \(\mathsf{S}\) low (from its default high) sets \(\mathsf{Q}\) to \(\mathsf{1}\), entering the Set state. The timing diagram advances one step to reflect these updates.

Timestep \(\mathsf{t_2}\): Hold State

Advancing to timestep \(\mathsf{t_2}\), input \(\mathsf{S}\) returns to \(\mathsf{1}\), indicated by the star to signal the analysis starting point. Here, \(\mathsf{S=1}\) paired with \(\mathsf{\overline{Q}=0}\) maintains \(\mathsf{Q}\) at \(\mathsf{1}\), which in turn holds \(\mathsf{\overline{Q}}\) at \(\mathsf{0}\). As a result, the outputs remain unchanged from the prior state despite the shift in \(\mathsf{S}\), embodying the hold state triggered when both \(\mathsf{S}\) and \(\mathsf{R}\) are \(\mathsf{1}\). This illustrates the SR latch’s memory function: the current hold state yields the opposite output from \(\mathsf{t_0}\) (also a hold state), proving that results depend not just on inputs but also on retained history. The timing diagram progresses by one timestep to capture this stability.

Timestep \(\mathsf{t_3}\): Reset State

At timestep \(\mathsf{t_3}\), the initial change occurs as input \(\mathsf{R}\) drops to \(\mathsf{0}\), highlighted by the star box. With \(\mathsf{Q}\) still at \(\mathsf{1}\), this \(\mathsf{R=0}\) drives \(\mathsf{n2}\)’s output (\(\mathsf{\overline{Q}}\)) high to \(\mathsf{1}\). The new \(\mathsf{1}\) propagates to \(\mathsf{n1}\)’s input, where \(\mathsf{S=1}\), forcing \(\mathsf{Q}\) low to \(\mathsf{0}\). Now with \(\mathsf{Q=0}\), the circuit enters the Reset state, activated by pulling \(\mathsf{R}\) from its default high. The timing diagram advances one step to reflect this transition.

Timestep \(\mathsf{t_4}\): Forbidden State

At timestep \(\mathsf{t_4}\), the circuit enters the forbidden state, where both inputs \(\mathsf{S}\) and \(\mathsf{R}\) are asserted low to \(\mathsf{0}\)—unlike the standard set or reset operations, which assert only one input low. Building on \(\mathsf{R}\) already at \(\mathsf{0}\) from \(\mathsf{t_3}\), the key transition, marked by the star box, occurs as \(\mathsf{S}\) drops to \(\mathsf{0}\). With \(\mathsf{\overline{Q}}\) still at \(\mathsf{1}\), this forces \(\mathsf{Q}\) high to \(\mathsf{1}\). The resulting \(\mathsf{Q=1}\), combined with \(\mathsf{R=0}\), then holds \(\mathsf{\overline{Q}}\) at \(\mathsf{1}\), stabilizing the outputs in this invalid configuration. Notably, both \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\) are now \(\mathsf{1}\), violating their expected complementary relationship, which is why asserting both inputs low is prohibited. The timing diagram advances one step to illustrate this anomaly.

Timestep \(\mathsf{t_5}\): Unknown State

At timestep \(\mathsf{t_5}\), an intriguing issue arises when attempting to restore inputs \(\mathsf{S}\) and \(\mathsf{R}\) to their default high state of \(\mathsf{1}\) following the forbidden state. Both inputs transition simultaneously, denoted by star boxes on \(\mathsf{S}\) and \(\mathsf{R}\). In practice, one input may lag slightly behind the other, or even with perfect simultaneity, inherent gate delays—arising from manufacturing variations—cause one NAND gate to respond faster than the other. On an integrated circuit with millions of gates, predicting which gate in the latch is quicker is impossible.

Assuming \(\mathsf{n1}\) reacts first: with \(\mathsf{S}\) rising to \(\mathsf{1}\) and \(\mathsf{\overline{Q}}\) still at \(\mathsf{1}\), it outputs \(\mathsf{Q=0}\); this \(\mathsf{Q=0}\) then feeds into \(\mathsf{n2}\) (with \(\mathsf{R=1}\)), yielding \(\mathsf{\overline{Q}=1}\) and stabilizing the circuit at \(\mathsf{Q=0, \overline{Q}=1}\).

Conversely, if \(\mathsf{n2}\) acts quicker: with \(\mathsf{R=1}\) and the prior \(\mathsf{Q=1}\), it drives \(\mathsf{\overline{Q}}\) low to \(\mathsf{0}\); the new \(\mathsf{\overline{Q}=0}\) then reaches \(\mathsf{n1}\) (with \(\mathsf{S=1}\)), producing \(\mathsf{Q=1}\) and locking in \(\mathsf{Q=1, \overline{Q}=0.}\)

This race condition yields entirely opposite stable states, depending on subtle timing and gate characteristics, rendering the outputs unpredictable and indeterminate (marked as \(\mathsf{X}\) in the timing diagram). To avoid such unreliable behavior in subsequent transitions, the forbidden state must always be circumvented.

Truth Table, or Rather the State Transition Table of a Basic SR Latch Implemented using NAND Gates

To describe the behavior of a basic SR latch implemented with NAND gates, we list the next-state outputs against all input combinations in a state transition table (also called a state table). Unlike the truth tables used for combinational circuits—which map inputs directly to outputs—state tables account for the memory in sequential elements like latches and flip-flops. Here, the same inputs can yield different outputs depending on the current state, so the table defines the next state at time \(\mathsf{t+1}\), denoted \(\mathsf{Q(t+1),}\) based on the inputs (\(\mathsf{S}\) and \(\mathsf{R}\)) and the present state \(\mathsf{Q(t)}\). This captures how the latch evolves over time. The state transition table for the NAND-based SR latch appears in the accompanying figure.

The rows above the pink margin in the table represent allowed input combinations, while those below indicate forbidden ones. In the hold state (\(\mathsf{S=1, R=1}\)), the outputs retain their previous values: \(\mathsf{Q(t+1) = Q(t)}\) and \(\mathsf{\overline{Q(t+1)} = \overline{Q(t)}.}\) To enter the set state, momentarily pull \(\mathsf{S}\) low to \(\mathsf{0}\) (yielding \(\mathsf{Q(t+1)=1, \overline{Q(t+1)}=0}\)), then return it to \(\mathsf{1}\) to hold the new state until further changes. Similarly, for reset, briefly assert \(\mathsf{R}\) low to \(\mathsf{0}\) (producing \(\mathsf{Q(t+1)=0, \overline{Q(t+1)}=1}\)), followed by restoring \(\mathsf{R}\) to \(\mathsf{1}\) to maintain the hold. The forbidden combination (\(\mathsf{S=0, R=0}\)) forces both outputs high (\(\mathsf{Q(t+1)=1, \overline{Q(t+1)}=1}\)), violating their complementary nature; moreover, transitioning back to default inputs from this state results in indeterminate outputs due to timing races.

Gated SR Latch

A gated NAND SR latch builds upon the basic NAND SR latch by incorporating an enable mechanism to control when the latch responds to its set and reset inputs. As illustrated in the figure, it consists of the core cross-coupled NAND gates, but with an additional pair of NAND gates that gate the \(\mathsf{S}\) and \(\mathsf{R}\) signals through a clock enable (\(\mathsf{CE}\)) input. The cross-coupled gates now receive their inputs from these outer NAND gates, ensuring that the latch remains transparent to \(\mathsf{S}\) and \(\mathsf{R}\) only when \(\mathsf{CE}\) is asserted.

When \(\mathsf{CE = 0}\), the outer NAND gates force both effective inputs to the cross-coupled pair to logic \(\mathsf{1}\), regardless of the actual \(\mathsf{S}\) and \(\mathsf{R}\) values—effectively holding the latch in its previous state and isolating it from external changes. For reliable operation in this mode, the \(\mathsf{S}\) and \(\mathsf{R}\) inputs should be held at their inactive level of \(\mathsf{0}\) (in contrast to the basic NAND SR latch, where \(\mathsf{0}\) is the active level). Upon transitioning \(\mathsf{CE}\) to \(\mathsf{1}\), the latch becomes responsive: the effective inputs reflect the logic of \(\mathsf{S}\) and \(\mathsf{R}\) (with \(\mathsf{S=1}\) asserting set and \(\mathsf{R=1}\) asserting reset), allowing the outputs \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\) to transition to set (\(\mathsf{Q=1, \overline{Q}=0}\)), reset (\(\mathsf{Q=0, \overline{Q}=1}\)), or hold states as determined by the input combination.

Based on the input combinations, the output could be in one of the following states:

This design prevents unintended state changes during inactive periods, making it suitable for clocked or synchronized applications.

Analysis of a Gated SR Latch

Given our detailed prior analysis of the basic SR latch, we will not revisit the operation of the cross-coupled NAND gates \(\mathsf{n1}\) and \(\mathsf{n2}\). Instead, this section will examine the effects of varying the clock enable (\(\mathsf{CE}\)) signal, particularly how it influences the inputs to the gating NAND gates \(\mathsf{n3}\) and \(\mathsf{n4}\), and in turn, the resulting states of the latch outputs.

Timesteps \(\mathsf{t_0-t_5}\): Hold State

During the time interval from \(\mathsf{t_0}\) to \(\mathsf{t_5}\), the \(\mathsf{CE}\) signal is held at logic \(\mathsf{0}\). This forces one input to each of the NAND gates \(\mathsf{n3}\) and \(\mathsf{n4}\) to remain at \(\mathsf{0}\), causing both gates to output a constant logic \(\mathsf{1}\). Consequently, the internal signals \(\mathsf{S_{int}}\) and \(\mathsf{R_{int}}\) are maintained at \(\mathsf{1}\), preventing any transitions in the latch outputs \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\). Thus, the gated SR latch stays in its hold state throughout the period when \(\mathsf{CE = 0}\).

Timesteps \(\mathsf{t_6-t_{11}}\):

From timesteps \(\mathsf{t_6}\) to \(\mathsf{t_{11}}\), the \(\mathsf{CE}\) signal is asserted at logic \(\mathsf{1}\), enabling the latch outputs to respond to variations in the \(\mathsf{S}\) and \(\mathsf{R}\) inputs. With both \(\mathsf{S}\) and \(\mathsf{R}\) held at \(\mathsf{0}\) during this period, the outputs of NAND gates \(\mathsf{n3}\) and \(\mathsf{n4}\) remain at \(\mathsf{1}\), preserving the hold state of the latch.

To set the output, \(\mathsf{S}\) is pulsed high to \(\mathsf{1}\) at \(\mathsf{t_7}\), driving the output of \(\mathsf{n3}\) low to \(\mathsf{0}\). This asserts \(\mathsf{S_{int} = 0,}\) which in turn forces \(\mathsf{Q}\) to transition to \(\mathsf{1}\) and \(\mathsf{\overline{Q}}\) to \(\mathsf{0}\), establishing the set state.

For reset operation, starting from the hold state, \(\mathsf{R}\) is pulsed high to \(\mathsf{1}\) at \(\mathsf{t_9}\). This causes \(\mathsf{n4}\) to output \(\mathsf{0}\), asserting \(\mathsf{R_{int} = 0}\) and triggering the cross-coupled gates such that the output of \(\mathsf{n1}\) goes low to \(\mathsf{0}\) (resetting \(\mathsf{Q}\)) while the output of \(\mathsf{n2}\) rises to \(\mathsf{1}\) (setting \(\mathsf{\overline{Q}}\)).

At \(\mathsf{t_{10}}\), however, both \(\mathsf{S}\) and \(\mathsf{R}\) are simultaneously driven to \(\mathsf{1}\)—an invalid input combination for the SR latch. This forces both \(\mathsf{S_{int}}\) and \(\mathsf{R_{int}}\) low to \(\mathsf{0}\), resulting in \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\) both transitioning to \(\mathsf{1}\), the forbidden metastable state. Subsequently, at \(\mathsf{t_{11}}\), akin to the behavior observed at \(\mathsf{t_5}\) in the basic NAND SR latch, the final output state becomes indeterminate and may settle unpredictably based on propagation delays and noise.

Timing Diagram

The timing diagram spanning the entire duration is depicted here. It illustrates that the latch outputs remain stable and unchanged whenever \(\mathsf{CE}\) is held at logic \(\mathsf{0}\). To induce a transition to either the set or reset state, the \(\mathsf{CE}\) signal must be at \(\mathsf{1}\) while the desired input—\(\mathsf{S}\) for set or \(\mathsf{R}\) for reset—is briefly pulsed high and then restored to its inactive default of \(\mathsf{0}\). In the gated NAND SR latch, the forbidden condition arises when both \(\mathsf{S}\) and \(\mathsf{R}\) are asserted to \(\mathsf{1}\) simultaneously with \(\mathsf{CE }\) at \(\mathsf{1}\); upon subsequently deasserting them both to \(\mathsf{0}\), the circuit enters an unpredictable, metastable state where the outputs cannot be reliably determined.

State Transition Table of a Gated SR Latch Implemented using NAND Gates

The rows above the pink margin in the table denote allowed input combinations, while those below signify forbidden ones. With \(\mathsf{CE=0}\) (regardless of \(\mathsf{S}\) and \(\mathsf{R}\)), the outputs hold their prior values: \(\mathsf{Q(t+1) = Q(t)}\) and \(\mathsf{\overline{Q(t+1)} = \overline{Q(t)}.}\) When \(\mathsf{CE=1}\) and \(\mathsf{S=0, R=0,}\) the hold state persists similarly. To set the output, assert \(\mathsf{CE=1}\) and pulse \(\mathsf{S}\) high to \(\mathsf{1}\) (yielding \(\mathsf{Q(t+1)=1, \overline{Q(t+1)}=0}\)), then return \(\mathsf{S}\) to \(\mathsf{0}\) to maintain the state. For reset, with \(\mathsf{CE=1,}\) briefly drive \(\mathsf{R}\) to \(\mathsf{1}\) (producing \(\mathsf{Q(t+1)=0, \overline{Q(t+1)}=1}\)), followed by restoring \(\mathsf{R}\) to \(\mathsf{0}\). The forbidden case (\(\mathsf{CE=1, S=1, R=1}\)) drives both outputs high (\(\mathsf{Q(t+1)=1, \overline{Q(t+1)}=1}\)), breaching complementarity; reverting to default inputs then yields indeterminate outputs from race conditions.

Symbol of Gated NAND SR Latch

The symbol of a gated SR latch based on NAND gates is shown here. If more features like active-low or active-high hard reset are added to it, then the symbol is updated to include the corresponding inputs.

Comparison of Gated and Basic NAND SR Latches

When comparing the gated NAND SR latch to its basic counterpart, a key enhancement emerges in output stability: state transitions require the \(\mathsf{CE}\) signal to be asserted high (to \(\mathsf{1}\)), thereby preventing unintended changes during inactive periods. Nevertheless, it retains the inherent drawback of the basic design, namely the risk of entering a forbidden state (both outputs high) followed by an indeterminate outcome upon input deassertion.

FAQs

Can we implement a latch using AND/OR or XOR/XNOR gates only?

A fundamental, standalone SR latch cannot be practically implemented using only two cross-coupled AND, OR, XOR, or XNOR gates. The core feedback mechanism requires the inherent inversion property of NAND or NOR gates to create stable, bistable operation for the Set, Reset, and Hold states.

Why are AND/OR and XOR/XNOR unsuitable?

• AND/OR Gates: In a simple cross-coupled configuration, they fail to produce any stable, complementary state. They typically deadlock (both outputs at 0 or 1) instead of holding a valid bit.
• XOR/XNOR Gates: When cross-coupled, they do not function as a standard memory cell. Their behavior is more akin to an oscillator or a toggle circuit, making them unsuitable for the core of a simple SR latch which is designed for stable state storage.

How does SR latch get first outputs?

An SR latch has no predetermined initial state when powered on – it enters a metastable condition. The initial state is determined by:

1. Circuit asymmetries – tiny manufacturing variations that make one gate slightly faster
2. Electrical noise at power-up that pushes the circuit toward one state
3. Actual input signals applied after power-up that force it to a defined state

This indeterminate startup is why practical circuits often include power-on reset circuits to initialize memory elements.