Latch v Flip-flop
A latch is a level-sensitive, fundamental bistable memory circuit that stores one bit of data. Its state is transparently controlled by its input signals while the control (enable) signal is active, whereas, a flip‑flop is an edge‑triggered bistable memory circuit that stores one bit of data.
Unlike a latch, which is level‑sensitive and transparent while the enable signal is active, a flip‑flop changes state only at a specific clock transition (rising or falling edge, also called, positive-edge or negative-edge, or simply posedge or negedge).
Comparison of Timing Diagrams of D Latches, D Flip-flops and T Flip-flops
This image compares output waveforms for key digital logic sequential circuits using the same input signal. See how D latches, D flip-flops, and T flip-flops perform, with a detailed breakdown of each device to follow.
Timing Diagrams of D Latches
Timing Diagrams of D Latch with Active-High Enable
In this active-high D latch, the output follows the input whenever the enable is at level \(\mathsf{1}\). The remaining intervals act as “hold zones”—highlighted in blue for easy analysis—where the circuit retains its previous value. Because the starting state is unknown, the initial \(\mathsf{0-10\,ns}\) hold zone is represented as an unknown signal, X.
Timing Diagrams of D Latch with Active-Low Enable
In this active-low D latch, the output follows the input whenever the enable is at level \(\mathsf{0}\). The remaining intervals serve as “hold zones”—highlighted in blue for easy analysis—where the circuit retains its previous value.
Timing Diagrams of D Flip-flops
Timing Diagrams of D Flip-flop Triggered at posedge
A positive-edge-triggered D flip-flop updates its output to match the input only at exact clock edges, marked by blue upward arrowheads at \(\mathsf{10, 30, 50, 70,}\) and \(\mathsf{90\,ns}\). Because the circuit holds its value at all other times, the background is entirely blue. Since the starting state is unknown, the initial output from \(\mathsf{0}\) to \(\mathsf{10\,ns}\) is represented as an unknown signal, X.
Timing Diagrams of D Flip-flop Triggered at negedge
A negative-edge-triggered D flip-flop updates its output to match the input only at clock falling edges, marked by pink downward arrowheads at \(\mathsf{0, 20, 40, 60, 80,}\) and \(\mathsf{100\,ns}\). Because the circuit holds its value at all other times, the background is blue. The initial \(\mathsf{0-20\,ns}\) output is shown as an unknown signal, X, because the prior input state is missing—introducing the concept of setup time, which we will explore later.
Timing Diagrams of T Flip-flops
Timing Diagrams of T Flip-flop Triggered at posedge
A positive-edge-triggered T flip-flop updates its output only at clock edges, marked by blue upward arrowheads at \(\mathsf{10, 30, 50, 70,}\) and \(\mathsf{90\,ns}\). Depending on the input, the circuit either holds its value (\(\mathsf{T=0,}\) shown in blue) or flips to the opposite state (\(\mathsf{T=1,}\) shown in pink). A valid starting state is required from \(\mathsf{0-10\,ns}\); if the initial output is an unknown X, all subsequent outputs will also remain X.
Timing Diagrams of T Flip-flop Triggered at negedge
A negative-edge-triggered T flip-flop updates its output only at clock falling edges, marked by pink downward arrowheads at \(\mathsf{0, 20, 40, 60, 80,}\) and \(\mathsf{100\,ns}\). At these instants, the circuit holds its previous value if \(\mathsf{T=0}\) (blue background) or toggles to its complement if \(\mathsf{T=1}\) (pink background). A valid starting value—such as \(\mathsf{1}\) from \(\mathsf{0-20\,ns}\)—is required first; if the initial output is an unknown X, all subsequent outputs will also remain X.
