What is a Flip-flop?
A flip‑flop is an edge‑triggered bistable memory circuit that stores one bit of data. Unlike a latch, which is level‑sensitive and transparent while the enable signal is active, a flip‑flop changes state only at a specific clock transition (rising or falling edge, also called, positive-edge or negative-edge, or simply posedge or negedge).
This synchronization with the clock makes flip‑flops the fundamental building blocks of sequential logic, ensuring predictable timing and eliminating transparency issues.
What is a D flip-flop?
A D (Data) flip-flop is a clocked bistable memory element designed to store one bit of data. It has a single input, D, and two complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)). The output state updates only at the chosen clock edge (posedge or negedge), capturing the value of \(\mathsf{D}\). Between clock transitions, the outputs remain stable, holding the stored state until the next clock event.
Symbolic Representation of a D Flip-flop
The symbol for a D flip-flop shows a single data input \(\mathsf{D}\), a clock input clk, and two complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)).
- The clock input is attached at a small notch on the symbol, indicating that the device is clock‑controlled.
- For a positive‑edge triggered D flip‑flop, the clock port is marked with a straight line entering the notch, showing that the output updates on the rising edge of the clock.
- For a negative‑edge triggered D flip‑flop, the clock port carries a bubble at the notch, denoting that the output updates on the falling edge of the clock.
- The outputs remain stable between clock transitions, holding the stored bit until the next active edge.
State Table of a D Flip-flop
This concise representation highlights the deterministic nature of the D flip‑flop: the next state always equals the data input at the clock edge, with no ambiguity or forbidden states.
Timing Diagram of a D Flip-flop
The timing diagram illustrates the behavior of a D flip‑flop with respect to its clock input. The signals shown are the clock (clk), the data input (\(\mathsf{D}\)), and the complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)).
- At each rising edge (
posedge) of the clock, the flip‑flop samples the value present at \(\mathsf{D}\) and transfers it to the output \(\mathsf{Q}\). - The complementary output \(\mathsf{\overline{Q}}\) simultaneously takes the opposite value.
- The rising edge at time step \(\mathsf{t_1}\) sees 1 presented at the input \(\mathsf{D}\) and so the output changes to 1 for the full cycle.
- At \(\mathsf{t_3}\), \(\mathsf{D=0}\) and hence, the output goes down to 0 for the complete clock cycle.
- Between clock edges, the outputs remain stable, holding the last captured state regardless of changes at the data input.
This diagram emphasizes the edge‑triggered nature of the D flip‑flop: only at the positive clock transition does the input affect the outputs. Any changes in \(\mathsf{D}\) while the clock is low or high (but not transitioning) have no immediate effect, ensuring predictable and synchronized operation in sequential circuits.
Hardware Implementation of a D Flip-flop
D flip‑flops can be realized through multiple circuit implementations. One of the simplest approaches uses two D latches arranged in a master–slave configuration, producing an edge‑triggered device. Another common design avoids latches altogether and instead employs a network of six NAND gates to achieve the same flip‑flop functionality. In practice, additional control inputs such as reset or enable are often incorporated into these structures, making the D flip‑flop more versatile and reliable than a bare‑bones implementation.
D Flip-flop through D Latches in Master-Slave Configuration
Positive-edge Triggered
The master–slave configuration of a positive‑edge triggered D flip‑flop uses two D latches connected in series, controlled by opposite phases of the clock. When the clock is low, the master latch is enabled and can follow the input \(\mathsf{D}\), while the slave latch is disabled and holds its state. When the clock transitions high, the master becomes disabled (its output fixed), and the slave is enabled, sampling the master’s output. This ensures that the external output \(\mathsf{Q}\) only updates at the rising edge of the clock, remaining stable for the entire cycle and providing true edge‑triggered behavior.
Negative-edge Triggered
The master–slave configuration of a negative‑edge triggered D flip‑flop also uses two D latches controlled by opposite phases of the clock. When the clock is high, the master latch is enabled and follows the input \(\mathsf{D}\), while the slave latch is disabled and holds its state. As the clock transitions low, the master becomes disabled (its output fixed), and the slave is enabled, sampling the master’s output. This ensures that the external output \(\mathsf{Q}\) updates only at the falling edge of the clock, remaining stable for the rest of the cycle and providing reliable edge‑triggered operation.
D Flip-flop through a Network of 6 NAND Gates
In the six‑NAND gate D flip‑flop, the outputs are controlled by how the NAND network responds to the clock and data input.
When the clock is low, the NAND gates that generate the effective set (\(\mathsf{S}\)) and reset (\(\mathsf{R}\)) inputs of the underlying SR latch (gates \(\mathsf{n1}\) and \(\mathsf{n2}\)) are forced to logic 1. This keeps both \(\mathsf{S}\) and \(\mathsf{R}\) inactive, so the latch holds its previous state unchanged.
At the rising edge of the clock, the gating opens and the state of \(\mathsf{D}\) determines whether the latch sets or resets:
- If \(\mathsf{D=0}\): The bottom NAND (\(\mathsf{n3}\)) remains at 1, which propagates through the three‑input NAND (\(\mathsf{n4}\)) and the upper NAND (\(\mathsf{n6}\)). This combination drives \(\mathsf{R=0}\), forcing the latch output \(\mathsf{Q}\) to 0. The feedback ensures that even if \(\mathsf{D}\) changes after the edge, the outputs remain stable while the clock is high.
- If \(\mathsf{D=1}\): The bottom NAND (\(\mathsf{n3}\)) switches to 0, which alters the inputs of \(\mathsf{n4}\) and \(\mathsf{n6}\). This produces \(\mathsf{S=0}\), activating the set condition and driving \(\mathsf{Q=1}\). Again, the feedback locks the outputs so that subsequent changes in \(\mathsf{D}\) during the high clock level cannot disturb the stored state.
Thus, the circuit ensures that the output \(\mathsf{Q}\) updates only at the positive clock transition, reflecting the value of \(\mathsf{D}\) at that instant, and remains fixed until the next rising edge.