What is a Flip-flop?
A flip‑flop is an edge‑triggered bistable memory circuit that stores one bit of data. Unlike a latch, which is level‑sensitive and transparent while the enable signal is active, a flip‑flop changes state only at a specific clock transition (rising or falling edge, also called, positive-edge or negative-edge, or simply posedge or negedge).
This synchronization with the clock makes flip‑flops the fundamental building blocks of sequential logic, ensuring predictable timing and eliminating transparency issues.
What is a T flip-flop?
A T (Toggle) flip-flop is a clocked bistable memory element designed to store one bit of data. It has a single input, T, and two complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)). ). At the chosen clock edge (positive or negative), the output state updates depending on the value of \(\mathsf{T}\):
- If \(\mathsf{T=0}\), the output remains unchanged, holding the previous state.
- If \(\mathsf{T=1}\), the output toggles, switching from 0 to 1 or 1 to 0.
Between clock transitions, the outputs remain stable, holding the stored state until the next clock event.
Symbolic Representation of a T Flip-flop
The symbol for a T flip-flop shows a single data input \(\mathsf{T}\), a clock input clk, and two complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)).
- The clock input is attached at a small notch on the symbol, indicating that the device is clock‑controlled.
- For a positive‑edge triggered T flip‑flop, the clock port is marked with a straight line entering the notch, showing that the output updates on the rising edge of the clock.
- For a negative‑edge triggered T flip‑flop, the clock port carries a bubble at the notch, denoting that the output updates on the falling edge of the clock.
- The outputs remain stable between clock transitions, holding the stored bit until the next active edge.
State Table of a T Flip-flop
This concise representation highlights the toggle nature of the T flip‑flop: at the active clock edge, the next state depends on the input \(\mathsf{T}\). When \(\mathsf{T=0}\), the output simply holds its previous value, ensuring stability. When \(\mathsf{T=1}\), the output switches to the opposite of its current state, producing a controlled toggle. In this way, the T flip‑flop alternates or preserves its state deterministically, with no ambiguity, strictly governed by the clock edge.
Timing Diagram of a T Flip-flop
The timing diagram illustrates the behavior of a T flip‑flop with respect to its clock input. The signals shown are the clock (clk), the data input (\(\mathsf{D}\)), and the complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)).
- At each rising edge (
posedge) of the clock, the flip‑flop samples the value present at \(\mathsf{T}\) and either holds or toggles the previous output \(\mathsf{Q}\). If \(\mathsf{T=0}\), the next state is the same as the current one and when \(\mathsf{T=1}\), the next state is the opposite of the present state. - The present state needs to be known to be hold or toggled, as shown in the time step \(\mathsf{t_0\rightarrow{}t_1}\) in pink. If the present state is unknown, \(\mathsf{X}\), then all the next states also become unknown, \(\mathsf{X}\).
- At \(\mathsf{t_1}\), since \(\mathsf{T=1}\), the output toggles from 0 to 1.
- The rising edge at \(\mathsf{t_3}\) is presented with \(\mathsf{T=0}\) which means that the T flip-flop holds its previous value of 1.
- The complementary output \(\mathsf{\overline{Q}}\) simultaneously takes the opposite value.
- Between clock edges, the outputs remain stable, holding the last captured state regardless of changes at the data input.
This diagram emphasizes the edge‑triggered nature of the T flip‑flop: only at the positive clock transition does the input affect the outputs. Any changes in \(\mathsf{T}\) while the clock is low or high (but not transitioning) have no immediate effect, ensuring predictable and synchronized operation in sequential circuits.
Hardware Implementation of a T Flip-flop
A T flip‑flop can be implemented using a D flip‑flop by feeding the D input through an XOR gate. In this arrangement, the XOR takes the toggle signal \(\mathsf{T}\) and the current output \(\mathsf{Q}\) as its inputs, producing the next input to the D flip‑flop. The resulting expression is:
\[\mathsf{D=T\oplus{}Q=TQ’+T’Q}\]
At the clock edge, this ensures that when \(\mathsf{T=0}\), the XOR output equals the present state \(\mathsf{Q}\), so the flip‑flop holds its value. When \(\mathsf{T=1}\), the XOR output becomes the complement of \(\mathsf{Q}\), causing the flip‑flop to toggle. In this way, the XOR‑driven D flip‑flop cleanly replicates the state transition behavior of a T flip‑flop, updating only at the active clock edge and remaining stable between transitions.
