What is a Latch?
A latch is a level-sensitive, fundamental bistable memory circuit that stores one bit of data. Its state is transparently controlled by its input signals while the control (enable) signal is active.
What is a D Latch?
A D (Data or Delay) Latch is a practical bistable memory element, derived from the SR latch. It has a single data input (\(\mathsf{D}\)) and an enable/control input, with two complementary outputs (\(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\)). By internally constraining the SR latch, the D latch eliminates the forbidden input combination, ensuring reliable operation. When enabled, the output follows the data input; when disabled, it holds its previous state.
Evolution of an SR Latch: Continued
D Latch
A D latch builds upon the gated SR latch by constraining its inputs to eliminate the forbidden state. It consists of the same cross‑coupled NAND core, but the set and reset signals are driven from a single data input (\(\mathsf{D}\)) and its complement, gated through the clock enable (\(\mathsf{CE}\)). When \(\mathsf{CE=1}\), the latch becomes transparent: the output \(\mathsf{Q}\) follows the data input \(\mathsf{D}\), while \(\mathsf{\overline{Q}\) reflects its complement. When \(\mathsf{CE=0}\), both effective inputs are forced to logic \(\mathsf{1}\), isolating the latch and holding its previous state. By mapping \(\mathsf{S=D}\) and \(\mathsf{R=D}\), the D latch ensures valid operation without the unstable condition of simultaneous set and reset.
Based on the input combinations, the output could be in one of the following states:
- Hold State: No change in output.
- When \(\mathsf{CE = 0}\); Hold state is maintained for any value of D.
- Set and Reset State: Output \(\mathsf{Q = 1}\) in Set, and \(\mathsf{Q = 0}\) in Reset state. \(\mathsf{\overline{Q}}\) is complementary.
- When \(\mathsf{CE = 0}\); Set and Reset state cannot happen, unless already being held.
- When \(\mathsf{CE = 1}\); For Set, make \(\mathsf{D = 1}\), For Reset, make \(\mathsf{D = 0}\).
This design prevents unintended state changes during inactive periods, making it suitable for clocked or synchronized applications.
Analysis of a D Latch
Given our detailed prior analysis of the basic SR latch, we will not revisit the operation of the cross-coupled NAND gates \(\mathsf{n1}\) and \(\mathsf{n2}\). Instead, this section will examine the effects of varying the clock enable (\(\mathsf{CE}\)) signal, particularly how it influences the inputs to the gating NAND gates \(\mathsf{n3}\) and \(\mathsf{n4}\), and in turn, the resulting states of the latch outputs.
Timesteps \(\mathsf{t_0-t_4}\): Hold State
During the time interval from \(\mathsf{t_0}\) to \(\mathsf{t_2}\), the \(\mathsf{CE}\) signal is held at logic \(\mathsf{0}\). This forces one input to each of the NAND gates \(\mathsf{n3}\) and \(\mathsf{n4}\) to remain at \(\mathsf{0}\), causing both gates to output a constant logic \(\mathsf{1}\). Consequently, the internal signals \(\mathsf{S_{int}}\) and \(\mathsf{R_{int}}\) are maintained at \(\mathsf{1}\), preventing any transitions in the latch outputs \(\mathsf{Q}\) and \(\mathsf{\overline{Q}}\). Thus, the D latch stays in its hold state throughout the period when \(\mathsf{CE = 0}\).
Timesteps \(\mathsf{t_3\&{}t_{4}}\):
From timesteps \(\mathsf{t_3}\) and \(\mathsf{t_{4}}\), the \(\mathsf{CE}\) signal is asserted at logic \(\mathsf{1}\), enabling the latch outputs to respond to variations in the \(\mathsf{D}\) input. Because of the NOT gate attached to the D input, the NAND gates \(\mathsf{n3}\)and \(\mathsf{n4}\) receive complementary inputs and hence, never go into the forbidden state as was the case with basic and the gated SR latch.
To set the output, \(\mathsf{D}\) is pulsed high to \(\mathsf{1}\) at \(\mathsf{t_3}\), driving the output of \(\mathsf{n3}\) low to \(\mathsf{0}\). This asserts \(\mathsf{S_{int} = 0,}\) which in turn forces \(\mathsf{Q}\) to transition to \(\mathsf{1}\) and \(\mathsf{\overline{Q}}\) to \(\mathsf{0}\), establishing the set state.
For reset operation, \(\mathsf{D}\) is pulled down to \(\mathsf{0}\) at \(\mathsf{t_4}\). This causes \(\mathsf{n4}\) to output \(\mathsf{0}\), asserting \(\mathsf{R_{int} = 0}\) and triggering the cross-coupled gates such that the output of \(\mathsf{n1}\) goes low to \(\mathsf{0}\) (resetting \(\mathsf{Q}\)) while the output of \(\mathsf{n2}\) rises to \(\mathsf{1}\) (setting \(\mathsf{\overline{Q}}\)).
Timing Diagram
The timing diagram spanning the entire duration is depicted here. It illustrates that the latch outputs remain stable and unchanged whenever \(\mathsf{CE}\) is held at logic \(\mathsf{0}\). To induce a transition to either the set or reset state, the \(\mathsf{CE}\) signal must be at \(\mathsf{1}\) while the input signal \(\mathsf{D}\) is changed to desired output—\(\mathsf{D=1}\) for set or \(\mathsf{D=0}\) for reset.
State Transition Table of a D Latch Implemented using NAND Gates
With \(\mathsf{CE=0}\) (regardless of the value on \(\mathsf{D}\), the outputs hold their prior values: \(\mathsf{Q(t+1) = Q(t)}\) and \(\mathsf{\overline{Q(t+1)} = \overline{Q(t)}.}\). To set the output, assert \(\mathsf{CE=1}\) and pulse \(\mathsf{D}\) high to \(\mathsf{1}\) (yielding \(\mathsf{Q(t+1)=1, \overline{Q(t+1)}=0}\)). For reset, with \(\mathsf{CE=1,}\) briefly drive \(\mathsf{D}\) to \(\mathsf{0}\) (producing \(\mathsf{Q(t+1)=0, \overline{Q(t+1)}=1}\)).
Comparison of D and SR Latches
When comparing the D latch to any implementation of the SR latches, a key enhancement emerges in output stability: the output never goes into a forbidden state. Hold state is maintained by keeping \(\mathsf{CE=0}\) and when \(\mathsf{CE=1}\), the output signal \(\mathsf{Q}\) follows the input data \(\mathsf{D}\).
FAQs
Can we implement a latch using AND/OR or XOR/XNOR gates only?
A fundamental, standalone SR latch cannot be practically implemented using only two cross-coupled AND, OR, XOR, or XNOR gates. The core feedback mechanism requires the inherent inversion property of NAND or NOR gates to create stable, bistable operation for the Set, Reset, and Hold states.
Why are AND/OR and XOR/XNOR unsuitable?
- AND/OR Gates: In a simple cross-coupled configuration, they fail to produce any stable, complementary state. They typically deadlock (both outputs at 0 or 1) instead of holding a valid bit.
- XOR/XNOR Gates: When cross-coupled, they do not function as a standard memory cell. Their behavior is more akin to an oscillator or a toggle circuit, making them unsuitable for the core of a simple SR latch which is designed for stable state storage.
How does SR latch get first outputs?
An SR latch has no predetermined initial state when powered on – it enters a metastable condition. The initial state is determined by:
- Circuit asymmetries – tiny manufacturing variations that make one gate slightly faster
- Electrical noise at power-up that pushes the circuit toward one state
- Actual input signals applied after power-up that force it to a defined state
This indeterminate startup is why practical circuits often include power-on reset circuits to initialize memory elements.