Logical Behavior of an XNOR Gate

An XNOR gate behaves as the opposite of an XOR gate logically, and outputs \(\mathsf{0}\) when odd number of inputs is \(\mathsf{1}\). In the remaining cases (when even number of inputs is \(\mathsf{1}\)), the output is \(\mathsf{1}\). An XNOR gate has a minimum of \(\mathsf{2}\) inputs and \(\mathsf{1}\) output signal.

Representation of an XNOR Gate

In this section, we will explore the symbolic and mathematical representations commonly associated with the gate. Additionally, we will examine how the gate is modeled using Verilog HDL.

Symbolic Representation

The symbolic representation of all the logic gates may vary depending on regional or institutional standards. In the United States, the American National Standards Institute (ANSI) and the Military Standard (MIL-STD-806B) standardized a symbol while European organizations such as the International Electrotechnical Commission (IEC), particularly in IEC 60617, favor a rectangular symbol. The Institute of Electrical and Electronics Engineers (IEEE), through standards like IEEE Std 91-1984, closely aligns with ANSI conventions and plays a pivotal role in harmonizing gate symbols across international platforms. Other countries and standards bodies may adopt slight variations to meet local engineering norms, but the underlying function always remains universally understood.

American Symbol

The XNOR gate is commonly illustrated as a concave-tipped figure with an additional curved line trailing behind its input edge, visually similar to the XOR gate but distinguished by a small circular marker at its output—signifying logical negation. On the left side, two or more input signals converge toward the gate’s slightly tapered edge, evoking the same selective logic consideration.

European Symbol

In European engineering documentation, the XNOR gate is represented as a rectangular block, maintaining uniformity across circuit schematics. Input lines enter from the left, feeding into the gate, while a single output line exits to the right, indicating the result of the logical operation. The output line has an angled line attached to it showing the negation of the XOR gate.

IEEE Symbol

The gate’s visual representation aligns with the American ANSI style, most notably illustrated through the characteristic curved symbol with a double edge at the front—now marked with a trailing circle at its output to denote logical negation. Similar to the AND symbol, it appears slightly elongated compared to its ANSI counterpart, yet maintains the smooth, shield-like curvature.

Mathematical Representation

To represent the operation of an XNOR gate mathematically, we start with the mathematical XOR expression and apply negation to its result. While the XOR operation is commonly denoted using the plus symbol inside a circle (\(\mathsf{\oplus}\)), the XNOR gate adds a layer of inversion. For example, the expression \(\mathsf{\overline{A\oplus{}B}}\) or \(\mathsf{(A\oplus{}B})’\)indicates that the output will be true only when both of, \(\mathsf{𝖠}\) and \(\mathsf{𝖡}\), are same (whether true or false). If \(\mathsf{𝖠}\) and \(\mathsf{B}\) are input signals and the XNOR gate produces the output signal \(\mathsf{OUT}\), it can be expressed as:

\[
\begin{aligned}
\mathsf{OUT\,}&\mathsf{= \overline{A\oplus{}B}}\textsf{ or } \\
\mathsf{OUT\,}&\mathsf{= (A\oplus{}B)’}
\end{aligned}
\]

If another input \(\mathsf{C}\) is added, then:

\[
\begin{aligned}
\mathsf{OUT\,}&\mathsf{= \overline{A\oplus{}B\oplus{}C}}\textsf{ or } \\
\mathsf{OUT\,}&\mathsf{= (A\oplus{}B\oplus{}C)’}
\end{aligned}
\]

Verilog HDL Representation

In Verilog HDL, the XNOR gate combines the behavior of the XOR operation with negation. At the dataflow and higher abstraction levels, it is typically written using the (^~) or (~^) symbol between the operands. This symbol is called the Bitwise XNOR symbol. At the gate level, the XNOR gate is instantiated using the keyword xnor(<output>, <inputs>). Given two input signals, A and B, the XNOR gate produces an output signal OUT using the following logic (only the relevant code is shown).

assign OUT = A ^~ B; // dataflow coding, or
assign OUT = A ~^ B; // dataflow coding
xnor x1 (OUT, A, B); //gate-level coding

If another inputs \(\mathsf{C}\) and \(\mathsf{D}\) are added, then it could be coded as shown below. However, a common caveat arises when extending the XNOR symbol to multi-input configurations. Care must be taken to account for whether the number of inputs is odd or even, as this can lead to different output behavior. A detailed discussion of this is presented in the section titled Special Consideration with XNOR Gates in a Cascade.

assign OUT = ~(A ^~ B ^~ C); // dataflow coding, or
assign OUT = ~(A ~^ B ~^ C); // dataflow coding
assign OUT = A ^~ B ^~ C ^~ D; // dataflow coding, or
assign OUT = A ~^ B ~^ C ~^ D; // dataflow coding
xnor x2 (OUT, A, B, C, D); //gate-level coding

Truth Table of an XNOR Gate

A truth table is a structured way to show the output of a logical operation or digital circuit for every possible combination of input values. It’s a staple tool in boolean algebra, digital electronics, and computer science, especially when designing or analyzing logic gates and circuits.

A truth table, typically has input columns to the left, and to the right are the derived or output expressions. Each row in a truth table represents a unque set of input combination.

Truth tables for 2-, 3-, and 4-input XNOR gates are shown here.

Truth Table of a 2-Input XNOR Gate

The following truth table demonstrates the behavior of a basic 2-input XNOR gate, where the inputs are labeled \(\mathsf{A}\) and\(\mathsf{B}\), and the resulting output is represented as \(\mathsf{XNOR}\). This gate yields a low output (\(\mathsf{0}\)) when odd number of the inputs is high; otherwise, the output remains high, (\(\mathsf{1}\)). The table captures every possible combination of inputs along with their corresponding output values. The truth table is presented after the XNOR gate symbol that corresponds with the truth table.

Truth Table of a 3-Input XNOR Gate

The following truth table demonstrates the behavior of a basic 3-input XNOR gate, where the inputs are labeled \(\mathsf{A}\), \(\mathsf{B}\) and \(\mathsf{C}\), and the resulting output is represented as \(\mathsf{XOR}\). This gate yields a low output (\(\mathsf{0}\)) when odd number of the inputs is high; otherwise, the output remains high, (\(\mathsf{1}\)). The table captures every possible combination of inputs along with their corresponding output values. The truth table is presented after the XNOR gate symbol that corresponds with the truth table.

Truth Table of a 4-Input XNOR Gate

The following truth table demonstrates the behavior of a basic 4-input XOR gate, where the inputs are labeled \(\mathsf{A}\), \(\mathsf{B}\), \(\mathsf{C}\) and \(\mathsf{D}\), and the resulting output is represented as \(\mathsf{XNOR}\). This gate yields a low output (\(\mathsf{0}\)) when odd number of the inputs is high; otherwise, the output remains high, (\(\mathsf{1}\)). The table captures every possible combination of inputs along with their corresponding output values. The truth table is presented after the XNOR gate symbol that corresponds with the truth table.

Can we Implement Multi-Input Gate Using 2-Input Gates in a Cascade?

A gate cascade refers to a structured arrangement where multiple logic gates are connected in series or in levels, so the output of one gate feeds into the input of another. This is especially common when you need to implement complex logic using simpler, typically 2-input gates — like building a 4-input XOR using a cascade of 2-input XOR gates. This changes the timings and other characteristics of the gate but our goal is to analyze if the logical behavior remains the same?

Special Consideration with XNOR Gates in a Cascade

The XNOR gate holds a special place in digital logic due to its associative nature—meaning that reordering its inputs does not affect the final output. However, despite its associativity, the resulting output may not always conform to the expected behavior of an XNOR gate when scaled to multiple inputs.

Fundamentally, the XNOR gate is the inverse of the XOR gate and operates as an even parity detector—producing a high output when an even number of input signals are high. That said, when a 3-input XNOR gate is built using cascaded 2-input XNOR gates, the resulting output mimics that of a 3-input XOR gate. To restore the expected even-parity behavior, a final NOT gate must be applied to invert the XOR-like result.

This anomaly stems from how negation propagates through a series of XNOR operations. Interestingly, for 4-input XNOR gates implemented with cascaded 2-input XNORs, the negation effect cancels out, and the output aligns correctly with the even-parity definition—no additional inversion is needed.

Therefore, for odd-input XNOR gate constructions, a final inversion stage is required to preserve accurate parity detection. This parallels the implementation strategy used in NOR and NAND gates, but with a subtle distinction: XOR gates (or even XNORs) may be cascaded to construct multi-input XNOR behavior, as long as the input count and final inversion are carefully considered. For even-input configurations, cascading 2-input XNOR gates yields the correct output directly.

Implementing a 3-Input XNOR Gate Using 2-Input XNOR Gates

This circuit implements a 3-input XNOR gate using cascaded 2-input XNOR gates. As explained in the section Special Consideration with XNOR Gates in a Cascade, although the XNOR gate is associative—meaning that the order of inputs doesn’t affect the structural outcome—its cascaded behavior introduces a negation effect. Specifically, when a 3-input XNOR is implemented using 2-input XNOR gates in series, the resulting output must be further negated to achieve the correct even parity response. This inversion compensates for the inherent toggling caused by cascading XNOR gates.

Readers are encouraged to construct truth tables for the configuration and compare the outputs to those of a canonical 3-input XNOR gate. This verification demonstrates that implementing a multi-input XNOR gate as a cascade of 2-input gates requires constructing a sequence of XNOR or XOR gates followed by a single NOT gate.

Implementing a 4-Input XNOR Gate Using 2-Input XNOR Gates

This illustration demonstrates a 4-input XNOR gate constructed using cascaded 2-input XNOR gates. Two implementations are provided: one with two levels of cascading, and another using three distinct levels of 2-input gates. The XNOR gate is associative, meaning the order of input operations does not affect the final result. This property proves particularly useful when constructing multi-input XNOR configurations using simpler 2-input gates. In the case of a 4-input XNOR, when implemented via cascaded 2-input XNOR gates, the internal negations effectively cancel each other out. As a result, the output aligns perfectly with what one would expect from a canonical 4-input XNOR gate—accurately producing a high signal when an even number of inputs are high, consistent with its role as an even-parity detector.

Readers are encouraged to generate truth tables based on each configuration and compare them against the canonical 4-input XNOR gate to confirm the logical behavior. This verification demonstrates that implementing a multi-input XNOR gate as a cascade of 2-input gates requires constructing a sequence of XNOR gates.

Basic Quiz about XNOR Gates