Logical Behavior of an Inverter (NOT Gate)
A NOT gate, or an inverter, reverses the input signal, that is, it outputs \(\mathsf{1}\) when the input is \(\mathsf{0}\) and when the input is \(\mathsf{1}\)), the output is \(\mathsf{0}\). An NOT gate has \(\mathsf{1}\) input and \(\mathsf{1}\) output signal.
- A NOT Gate:
- Negates the input.
- Has \(\mathsf{1}\) input and \(\mathsf{1}\) output.
Representation of a NOT Gate
In this section, we will explore the symbolic and mathematical representations commonly associated with the gate. Additionally, we will examine how the gate is modeled using Verilog HDL.
Symbolic Representation
The symbolic representation of all the logic gates may vary depending on regional or institutional standards. In the United States, the American National Standards Institute (ANSI) and the Military Standard (MIL-STD-806B) standardized a symbol while European organizations such as the International Electrotechnical Commission (IEC), particularly in IEC 60617, favor a rectangular symbol. The Institute of Electrical and Electronics Engineers (IEEE), through standards like IEEE Std 91-1984, closely aligns with ANSI conventions and plays a pivotal role in harmonizing gate symbols across international platforms. Other countries and standards bodies may adopt slight variations to meet local engineering norms, but the underlying function always remains universally understood.
American Symbol
The NOT gate, in American symbol style, is depicted as a triangle pointing right with a small circle (bubble) at its output tip (to negate the buffer). The single input enters at the left side of the triangle, representing the source signal. The triangle implies signal directionality, while the bubble denotes logical inversion—outputting a high (true) value only when the input is low (false).
European Symbol
In European engineering documentation, the NOT gate is represented by a simple rectangular block with a single input entering from the left and a single output exiting on the right. The output line has an angled line attached to it showing the negation of the Buffer.
IEEE Symbol
The gate’s visual representation aligns with the American ANSI style, depicted as a triangle pointing right with a small output bubble. In IEEE diagrams, the symbol is typically more elongated than its ANSI counterpart, emphasizing directional flow. The output bubble signifies inversion, defining its role as a unary operator that flips logical state.
Mathematical Representation
The NOT gate is mathematically represented using either an overline (\(\mathsf{\overline{\phantom{A}}}\)) or a prime symbol (\(\mathsf{′}\)), each denoting logical negation of its single input. If the input signal is \(\mathsf{𝖠}\), the inverted output can be expressed as \(\mathsf{\overline{A}}\) when using the overline notation, or a \(\mathsf{A’}\) when using the prime notation—both conveying that the output becomes high (true) only when the input is low (false). Overline notation is favored in visual schematics and formal Boolean algebra expressions, while the prime symbol often appears in typed or linear formats where rendering overlines is impractical.
\[\mathsf{OUT= \overline{A}=A’} \]
Verilog HDL Representation
In Verilog HDL, the ~ symbol is used to represent the NOT operation, formerly called the Bitwise NOT operation at the dataflow and higher abstraction levels. At the gate level, the NOT gate is instantiated using the keyword not(<output>, <input>). Given an input signal, A, the NOT gate produces an output signal OUT using the following logic (only the relevant code is shown).
assign OUT = ~A; // dataflow coding not n1 (OUT, A); //gate-level coding
Truth Table of a NOT Gate
A truth table is a structured way to show the output of a logical operation or digital circuit for every possible combination of input values. It’s a staple tool in boolean algebra, digital electronics, and computer science, especially when designing or analyzing logic gates and circuits.
A truth table, typically has input columns to the left, and to the right are the derived or output expressions. Each row in a truth table represents a unque set of input combination.
The following truth table demonstrates the behavior of a NOT gate, where the input is labeled \(\mathsf{A}\), and the resulting output is represented as \(\mathsf{NOT}\). This gate yields a high output (\(\mathsf{1}\)) for a low input and vice versa. The table captures every possible combination of input along with the corresponding output values. The truth table is presented after the NOT gate symbol that corresponds with the truth table.
