Logical Behavior of a NOR Gate

A NOR gate behaves as the opposite of an OR gate logically, and outputs \(\mathsf{0}\) when any input is \(\mathsf{1}\). In the only remaining case (when all inputs are \(\mathsf{0}\)), the output is \(\mathsf{1}\). A NOR gate has a minimum of \(\mathsf{2}\) inputs and \(\mathsf{1}\) output signal.

Representation of a NOR Gate

In this section, we will explore the symbolic and mathematical representations commonly associated with the gate. Additionally, we will examine how the gate is modeled using Verilog HDL.

Symbolic Representation

The symbolic representation of all the logic gates may vary depending on regional or institutional standards. In the United States, the American National Standards Institute (ANSI) and the Military Standard (MIL-STD-806B) standardized a symbol while European organizations such as the International Electrotechnical Commission (IEC), particularly in IEC 60617, favor a rectangular symbol. The Institute of Electrical and Electronics Engineers (IEEE), through standards like IEEE Std 91-1984, closely aligns with ANSI conventions and plays a pivotal role in harmonizing gate symbols across international platforms. Other countries and standards bodies may adopt slight variations to meet local engineering norms, but the underlying function always remains universally understood.

American Symbol

The NOR gate is commonly illustrated as a concave-tipped figure, visually similar to the OR gate but distinguished by a small circular marker at its output—signifying logical negation. On the left side, two or more input signals converge toward the gate’s slightly tapered edge, evoking the same inclusive logic consideration.

European Symbol

In European engineering documentation, the NOR gate is represented as a rectangular block, maintaining uniformity across circuit schematics. Input lines enter from the left, feeding into the gate, while a single output line exits to the right, indicating the result of the logical operation. The output line has an angled line attached to it showing the negation of the OR gate.

IEEE Symbol

The gate’s visual representation aligns with the American ANSI style, most notably illustrated through the characteristic curved symbol—now marked with a trailing circle at its output to denote logical negation. Similar to the AND symbol, it appears slightly elongated compared to its ANSI counterpart, yet maintains the smooth, shield-like curvature.

Mathematical Representation

To represent the operation of a NOR gate mathematically, we start with the mathematical OR expression and apply negation to its result. While the OR operation is commonly denoted using the plus symbol (+), the NOR gate adds a layer of inversion. For example, the expression \(\mathsf{\overline{A+B}}\) or \(\mathsf{(A+B})’\)indicates that the output will be true only when both inputs, \(\mathsf{𝖠}\) and \(\mathsf{𝖡}\), are false (or low). If \(\mathsf{𝖠}\) and \(\mathsf{B}\) are input signals and the NOR gate produces the output signal \(\mathsf{OUT}\), it can be expressed as:

\[
\begin{aligned}
\mathsf{OUT\,}&\mathsf{= \overline{A+B}}\textsf{ or } \\
\mathsf{OUT\,}&\mathsf{= (A+B)’}
\end{aligned}
\]

If another input \(\mathsf{C}\) is added, then:

\[
\begin{aligned}
\mathsf{OUT\,}&\mathsf{= \overline{A+B+C}}\textsf{ or } \\
\mathsf{OUT\,}&\mathsf{= (A+B+C)’}
\end{aligned}
\]

Verilog HDL Representation

In Verilog HDL, the NOR gate combines the behavior of the OR operation with negation. At the dataflow and higher abstraction levels, it is typically written using the negation (~) of bitwise OR symbol (|) between the operands to get the result. At the gate level, the NOR gate is instantiated using the keyword nor(<output>, <inputs>). Given two input signals, A and B, the NOR gate produces an output signal OUT using the following logic (only the relevant code is shown).

assign OUT = ~(A | B); // dataflow coding
nor n1 (OUT, A, B); //gate-level coding

If another input \(\mathsf{C}\) is added, then:

assign OUT = ~(A | B | C); // dataflow coding
nor n2 (OUT, A, B, C); //gate-level coding

Truth Table of a NOR Gate

A truth table is a structured way to show the output of a logical operation or digital circuit for every possible combination of input values. It’s a staple tool in boolean algebra, digital electronics, and computer science, especially when designing or analyzing logic gates and circuits.

A truth table, typically has input columns to the left, and to the right are the derived or output expressions. Each row in a truth table represents a unque set of input combination.

Truth tables for 2-, 3-, and 4-input NOR gates are shown here.

Truth Table of a 2-Input NOR Gate

The following truth table demonstrates the behavior of a basic 2-input NOR gate, where the inputs are labeled \(\mathsf{A}\) and\(\mathsf{B}\), and the resulting output is represented as \(\mathsf{NOR}\). This gate yields a low output (\(\mathsf{0}\)) when any of the inputs is high; otherwise, the output remains high, (\(\mathsf{1}\)). The table captures every possible combination of inputs along with their corresponding output values. The truth table is presented after the NOR gate symbol that corresponds with the truth table.

Truth Table of a 3-Input NOR Gate

The following truth table demonstrates the behavior of a basic 3-input NOR gate, where the inputs are labeled \(\mathsf{A}\), \(\mathsf{B}\) and \(\mathsf{C}\), and the resulting output is represented as \(\mathsf{OR}\). This gate yields a low output (\(\mathsf{0}\)) when any of the inputs is high; otherwise, the output remains high, (\(\mathsf{1}\)). The table captures every possible combination of inputs along with their corresponding output values. The truth table is presented after the NOR gate symbol that corresponds with the truth table.

Truth Table of a 4-Input NOR Gate

The following truth table demonstrates the behavior of a basic 4-input OR gate, where the inputs are labeled \(\mathsf{A}\), \(\mathsf{B}\), \(\mathsf{C}\) and \(\mathsf{D}\), and the resulting output is represented as \(\mathsf{NOR}\). This gate yields a low output (\(\mathsf{0}\)) when any of the inputs is high; otherwise, the output remains high, (\(\mathsf{1}\)). The table captures every possible combination of inputs along with their corresponding output values. The truth table is presented after the NOR gate symbol that corresponds with the truth table.

Can we Implement Multi-Input Gate Using 2-Input Gates in a Cascade?

A gate cascade refers to a structured arrangement where multiple logic gates are connected in series or in levels, so the output of one gate feeds into the input of another. This is especially common when you need to implement complex logic using simpler, typically 2-input gates — like building a 4-input OR using a cascade of 2-input OR gates. This changes the timings and other characteristics of the gate but our goal is to analyze if the logical behavior remains the same?

Implementing a 3-Input NOR Gate Using 2-Input NOR Gates

This circuit implements a 3-input NOR gate using cascaded 2-input NOR gates. Due to the non-associative nature of NOR logic, the behavior does not remain identical to a single 3-input gate, and input ordering does affect the final output. Readers are encouraged to construct truth tables for the configuration and compare the outputs to those of a canonical 3-input NOR gate. This verification demonstrates that implementing a multi-input NOR gate as a cascade of 2-input gates requires constructing a sequence of OR gates followed by a single NOT gate.

Implementing a 4-Input NOR Gate Using 2-Input NOR Gates

This illustration demonstrates a 4-input NOR gate constructed using cascaded 2-input NOR gates. Two implementations are provided: one with two levels of cascading, and another using three distinct levels of 2-input gates. Because NOR operations are non-associative, both versions produce logically different outputs. Readers are encouraged to generate truth tables based on each configuration and compare them against the canonical 4-input NOR gate to confirm different logical behavior. This verification demonstrates that implementing a multi-input NOR gate as a cascade of 2-input gates requires constructing a sequence of OR gates followed by a single NOT gate.

Basic Quiz about NOR Gates