How to Convert Other Logic Gates to Their NOR Equivalent?

NOR Gate Behavior: Quick Recap

A NOR gate behaves as the opposite of an OR gate logically, and outputs \(\mathsf{0}\) when any input is \(\mathsf{1}\). In the only remaining case (when all inputs are \(\mathsf{0}\)), the output is \(\mathsf{1}\). A NOR gate has a minimum of \(\mathsf{2}\) inputs and \(\mathsf{1}\) output signal.

IEEE symbol of a 2-input NAND gate and its truth table are shown here.

For a detailed discussion on NOR gates, please visit its dedicated page.

Logic Gate and Their Equivalent NOR Forms

In this section, we shall list all the equivalent circuits for each logic gate. Click the relevant link to directly arrive at the content for NOT->NOR, Buffer->NOR, OR->NOR, AND->NOR, NAND->NOR, XOR->NOR and XNOR->NOR conversion.

For the similar transformation for the NAND gates, visit the logic gates to their NAND equivalent page. For more options, visit the How to Convert to Equivalent NAND/NOR Schematics?

NOT and Its NOR Equivalent Form

The IEEE symbol and truth table of a NOT gate is given below. For a detailed understanding, please visit the NOT gate page.

This conversion is particularly interesting because the NOT gate operates on a single input, while NOR gates require at least two inputs. To bridge this difference, we simply duplicate the input—feeding the same signal into both inputs of the NOR gate—and observe the result. This clever trick allows us to mimic the behavior of a NOT gate using a two-input NOR gate.

Since we’re feeding the same input A into both inputs of the NOR gate, we effectively replace B in the NOR truth table with A. This means the entries for input combinations 01 and 10 become irrelevant, as both inputs are always identical. Focusing on the valid cases—00 and 11—we analyze the output by first considering the OR gate behavior, then inverting it to reflect the NOR operation. The OR output for inputs 00 and 11 mirrors the input A itself: 0 and 1, respectively. Inverting this gives us the NOR output \(\mathsf{Z=aoverline{A}}\), which successfully replicates the behavior of a NOT gate.

Buffer and Its NOR Equivalent Form

The IEEE symbol and truth table of a BUF gate is given below. For a detailed understanding, please visit the Buffer page.

The equivalent circuit of a Buffer using NOR gates is quite simple, as it consists of two inverters connected in sequence. The first NOR gate receives the same input on both of its terminals, producing the complement of that input. This inverted signal is then fed into both inputs of a second NOR gate, which inverts it again—resulting in the original input being restored at the output. This double inversion effectively replicates the behavior of a Buffer, using only NOR gates.

OR and Its NOR Equivalent Form

The IEEE symbol and truth table of an OR gate is given below. For a detailed understanding, please visit the OR gate page.

The conversion from OR to NOR is quite straightforward, since the OR gate’s output is simply the inverted result of a NOR operation. By applying a NOT gate to the output of a NOR gate, we recover the original OR behavior. And since we’ve already seen how to implement a NOT gate using a NOR gate with duplicated inputs, the final circuit becomes a two-stage NOR configuration: first performing the NOR operation, then inverting the result to emulate an OR gate.

AND and Its NOR Equivalent Form

The IEEE symbol and truth table of an AND gate is given below. For a detailed understanding, please visit the AND gate page.

To replicate the functionality of an AND gate using NOR gates, we rely on DeMorgan’s Law, which states that:

\[\mathsf{\overline{\left(A+B\right)}=\overline{A}\cdot{}\overline{B}}\]

This tells us that the output of a NOR gate is equivalent to the AND of the inverted inputs A and B. Therefore, if we invert both inputs before feeding them into a NOR gate, the resulting output will match the AND behavior of the original signals. We can verify it as:

\[\mathsf{\overline{\left( \overline{A} + \overline{B} \right)} = \overline{\overline{A}} \cdot{} \overline{\overline{B}} = A\cdot{}B}\]

Since we’ve already established how to implement NOT gates using NOR, this setup is straightforward: two NOR gates for inverting A and B, followed by a third NOR gate to produce the AND output.

However, this arrangement can be visually cluttered and unnecessarily long. To simplify, we often represent the inverted inputs with small bubbles at the entry points of the final NOR gate, indicating that A and B are being inverted before the NOR operation—effectively capturing the AND logic in a compact form.

This correctness of the conversion can also be verified from the truth table as well.

NAND and Its NOR Equivalent Form

The IEEE symbol and truth table of an NAND gate is given below. For a detailed understanding, please visit the NAND gate page.

A NAND gate using NOR gates is constructed by first applying the AND->NOR equivalence, which replicates the behavior of an AND gate using NOR logic. This is then followed by a NOT->NOR schematic to invert the AND output, completing the NAND functionality. The combination effectively mirrors the NAND gate’s logic using only NOR gates.

XOR and Its NOR Equivalent Form

The IEEE symbol and truth table of an XOR gate is given below. For a detailed understanding, please visit the XOR gate page.

The XOR gate cannot be directly converted into its NOR equivalent form. Instead, the NOR-based implementation is derived from the XOR gate’s expression in either its AND-OR or OR-AND equivalent circuit. To understand this better, one can refer to the solution that illustrates the AND-OR form, and another that explains the OR-AND form. Rather than providing a direct NOR replacement for XOR, we first express it in its Sum of Products or Product of Sums form, and then apply the appropriate NOR-based transformations using the known schematics for AND and OR gates built from NORs.

It’s also important to note that in problems requiring NOR-only circuits, the original circuit is typically presented in an AND-OR configuration—either standard or non-standard—which serves as the starting point for the conversion.

XNOR and Its NAND Equivalent Form

The IEEE symbol and truth table of an XNOR gate is given below. For a detailed understanding, please visit the XNOR gate page.

The XNOR gate, like the XOR gate, is not directly converted into its NOR equivalent form. Instead, its NOR-based implementation is derived from the original XNOR expression represented in either AND-OR or OR-AND form. For further clarity, refer to the XNOR gate’s implementation using Sum of Products (SOP) and Product of Sums (POS) forms on the relevant pages. These canonical forms serve as the foundation for converting the logic into NOR-only circuits using standard transformations for AND and OR gates built from NORs.

It’s also important to note that in problems requiring NOR-only circuits, the original circuit is typically presented in an AND-OR configuration—either standard or non-standard—which serves as the starting point for the conversion.