How to Convert a Logic Diagram to Its NOR-Only Equivalent?

How to Convert a Logic Diagram to Its NOR Equivalent?

The steps for converting a given function into its NOR-based equivalent circuit are outlined here.

If the original function is provided in Boolean form, or as a truth table, or in a schematic which includes NAND, XOR, or XNOR gates, it should first be translated into its AND-OR equivalent circuit. Once that standard form is established, the following steps can be applied to systematically transform it into a NOR-only implementation.

In this section, we’ll explore how to transform any given logical function into its NOR gate equivalent form. For converting a schematic into a NAND-based version, refer to its dedicated page. You can also click through to see how each basic gate is implemented using NAND and NOR gates. For broader strategies and examples, visit the page titled How to Convert to Equivalent NAND/NOR Schematics? to discover more options and techniques.

Why Use This Approach?

While replacing each gate with its NOR equivalent is a valid approach to convert a schematic, it can sometimes introduce unnecessary gates into the final circuit. These redundancies can often be avoided by applying the structured bubble-pushing method outlined above.

Best-Use Case

This method is most effective when the original schematic is given in standard Product of Sums (POS) form, as it naturally avoids introducing extra bubbles during conversion. That said, any circuit—regardless of its initial structure—can still be transformed into its NOR equivalent by following these steps.

Comparison with Converting to NOR Equivalent Circuit

In comparison, the key distinction in the NOR equivalence steps is that a bubble is added to the output of each OR gate and to the input of each AND gate. Beyond this adjustment, the overall procedure remains the same. See the solution with this approach and the final conclusion.

Example

To convert a logic diagram into its NOR equivalent form, we start by analyzing a circuit arranged in a non-standard configuration—neither in canonical Sum of Products nor in Product of Sums form. The circuit includes five inputs: \(\mathsf{A, B, C, D}\), and \(\mathsf{E}\). First, inputs \(\mathsf{A}\) and \(\mathsf{\overline{B}}\) are fed into an AND gate, which we’ll refer to as \(\mathsf{g_1}\), producing one intermediate output. Meanwhile, inputs \(\mathsf{\overline{C}}\) and \(\mathsf{D}\) enter an OR gate, labeled \(\mathsf{g_2}\), generating a second intermediate output. Next, the outputs of \(\mathsf{g_1}\) and \(\mathsf{g_2}\) become the inputs to another OR gate, named \(\mathsf{g_3}\). Then, the output of \(\mathsf{g_3}\) is combined with input \(\mathsf{E}\) at the inputs of a second AND gate, called \(\mathsf{g_4}\). Finally, \(\mathsf{g_4}\) produces the circuit’s output signal, denoted as \(\mathsf{Z}\). With this structure defined, we can now proceed to systematically replace each gate with its NOR-based equivalent, ensuring the entire circuit is expressed using only NOR gates.

Step 1

To enhance clarity and streamline the NOR conversion, a NOT gate—represented as a blue bubble—has been added:

• At the output of each OR gate, namely \(\mathsf{g_2}\) and \(\mathsf{g_3}\).
• At the input of each AND gate, namely \(\mathsf{g_1}\) and \(\mathsf{g_4}\).

Step 2

All wires have been checked for logic neutrality, and pink bubbles have been added where needed to cancel lone inversions.

• Bubble added to each wire connecting \(\mathsf{A}\) and \(\mathsf{\overline{B}}\) to the inputs of \(\mathsf{g_1}\).
• No bubble added to wires connecting \(\mathsf{\overline{C}}\) and \(\mathsf{D}\) to the inputs of \(\mathsf{g_2}\).
• A bubble added to the wire connecting \(\mathsf{E}\) to the input of \(\mathsf{g_4}\).
• No bubble added to the wire connecting output of \(\mathsf{g_1}\) to input of \(\mathsf{g_3}\).
• Bubble added near the input of \(\mathsf{g_3}\) to balance the one at \(\mathsf{g_2}\)’s output.
• No bubble added to the wire connecting output of \(\mathsf{g_3}\) to input of \(\mathsf{g_4}\) (bubbles cancel each other out).
• No bubble added to the wire connecting output of \(\mathsf{g_4}\) to output \(\mathsf{Z}\).

Step 3

All gates have been successfully replaced with their NOR equivalents. However, the additional bubbles introduced for logic balancing—shown in pink—remain in the circuit to preserve functional correctness. These bubbles represent necessary inversions that could not be canceled out and are implemented using NOR gates configured as NOT gates.

The bubbles originally connected to the input signals have been omitted, and the corresponding input literals have been inverted to reflect their effect (shown in pink). All remaining bubbles have been replaced with NOR-based inverters, ensuring the final circuit maintains logical equivalence using only NOR gates. The final circuit in NOR form is shown here.

Alternative Solution

Here we observe an alternative solution that bypasses the bubble-pushing method and instead directly replaces each gate with its NOR equivalent, as previously discussed.

Conclusion

At first glance, the resulting circuit may appear different, but upon closer inspection, both implementations are logically equivalent. This equivalence becomes clear when we analyze the role of the bubbles. While looking at the alternative solution:

• \(\mathsf{g_5}\) functions as a NOT gate and is same as the one in the final solution using the bubble-push method.
• The bubbles at the inputs of \(\mathsf{g_1}\) and the second input of \(\mathsf{g_4}\) are omitted in the bubble-push solution because the inputs themselves are inverted.
• The bubble at the first input of \(\mathsf{g_4}\) is cancelled out by the \(\mathsf{g_6}\) (which functions as a NOT gate).

Ultimately, both methods yield the same logical behavior. However, the bubble-push approach tends to produce a cleaner schematic by eliminating bubbles at the inputs of NOR gates, resulting in a more streamlined and visually intuitive design.