How to Convert Other Logic Gates to Their NAND Equivalent?

NAND Gate Behavior: Quick Recap

A NAND gate behaves as the opposite of an AND gate logically, and outputs \(\mathsf{0}\) when all inputs are \(\mathsf{1}\). In all other cases, the output is \(\mathsf{1}\). A NAND gate has a minimum of \(\mathsf{2}\) inputs and \(\mathsf{1}\) output signal.

IEEE symbol of a 2-input NAND gate and its truth table are shown here.

For a detailed discussion on NAND gates, please visit its dedicated page.

Logic Gate and Their Equivalent NAND Forms

In this section, we shall list all the equivalent circuits for each logic gate. Click the relevant link to directly arrive at the content for NOT->NAND, Buffer->NAND, AND->NAND, OR->NAND, NOR->NAND, XOR->NAND and XNOR->NAND conversion.

For the similar transformation for the NOR gates, visit the logic gates to their NOR equivalent page. For more options, visit the How to Convert to Equivalent NAND/NOR Schematics?

NOT and Its NAND Equivalent Form

The IEEE symbol and truth table of a NOT gate is given below. For a detailed understanding, please visit the NOT gate page.

This conversion is particularly interesting because the NOT gate operates on a single input, while NAND gates require at least two inputs. To bridge this difference, we simply duplicate the input—feeding the same signal into both inputs of the NAND gate—and observe the result. This clever trick allows us to mimic the behavior of a NOT gate using a two-input NAND gate.

Since we’re feeding the same input A into both inputs of the NAND gate, we effectively replace B in the NAND truth table with A. This means the entries for input combinations 01 and 10 become irrelevant, as both inputs are always identical. Focusing on the valid cases—00 and 11—we analyze the output by first considering the AND gate behavior, then inverting it to reflect the NAND operation. The AND output for inputs 00 and 11 mirrors the input A itself: 0 and 1, respectively. Inverting this gives us the NAND output \(\mathsf{Z=aoverline{A}}\), which successfully replicates the behavior of a NOT gate.

Buffer and Its NAND Equivalent Form

The IEEE symbol and truth table of a BUF gate is given below. For a detailed understanding, please visit the Buffer page.

The equivalent circuit of a Buffer using NAND gates is quite simple, as it consists of two inverters connected in sequence. The first NAND gate receives the same input on both of its terminals, producing the complement of that input. This inverted signal is then fed into both inputs of a second NAND gate, which inverts it again—resulting in the original input being restored at the output. This double inversion effectively replicates the behavior of a Buffer, using only NAND gates.

AND and Its NAND Equivalent Form

The IEEE symbol and truth table of an AND gate is given below. For a detailed understanding, please visit the AND gate page.

The conversion from AND to NAND is quite straightforward, since the AND gate’s output is simply the inverted result of a NAND operation. By applying a NOT gate to the output of a NAND gate, we recover the original AND behavior. And since we’ve already seen how to implement a NOT gate using a NAND gate with duplicated inputs, the final circuit becomes a two-stage NAND configuration: first performing the NAND operation, then inverting the result to emulate an AND gate.

OR and Its NAND Equivalent Form

The IEEE symbol and truth table of an OR gate is given below. For a detailed understanding, please visit the OR gate page.

To replicate the functionality of an OR gate using NAND gates, we rely on DeMorgan’s Law, which states that:

\[\mathsf{\overline{\left(AB\right)}=\overline{A}+\overline{B}}\]

This tells us that the output of a NAND gate is equivalent to the OR of the inverted inputs A and B. Therefore, if we invert both inputs before feeding them into a NAND gate, the resulting output will match the OR behavior of the original signals. We can verify it as:

\[\mathsf{\overline{\left( \overline{A} \cdot{} \overline{B} \right)} = \overline{\overline{A}} + \overline{\overline{B}} = A+B}\]

Since we’ve already established how to implement NOT gates using NAND, this setup is straightforward: two NAND gates for inverting A and B, followed by a third NAND gate to produce the OR output.

However, this arrangement can be visually cluttered and unnecessarily long. To simplify, we often represent the inverted inputs with small bubbles at the entry points of the final NAND gate, indicating that A and B are being inverted before the NAND operation—effectively capturing the OR logic in a compact form.

This correctness of the conversion can also be verified from the truth table as well.

NOR and Its NAND Equivalent Form

The IEEE symbol and truth table of an NOR gate is given below. For a detailed understanding, please visit the NOR gate page.

A NOR gate using NAND gates is constructed by first applying the OR->NAND equivalence, which replicates the behavior of an OR gate using NAND logic. This is then followed by a NOT->NAND schematic to invert the OR output, completing the NOR functionality. The combination effectively mirrors the NOR gate’s logic using only NAND gates.

XOR and Its NAND Equivalent Form

The IEEE symbol and truth table of an XOR gate is given below. For a detailed understanding, please visit the XOR gate page.

The XOR gate cannot be directly converted into its NAND equivalent form. Instead, the NAND-based implementation is derived from the XOR gate’s expression in either its AND-OR or OR-AND equivalent circuit. To understand this better, one can refer to the solution that illustrates the AND-OR form, and another that explains the OR-AND form. Rather than providing a direct NAND replacement for XOR, we first express it in its Sum of Products or Product of Sums form, and then apply the appropriate NAND-based transformations using the known schematics for AND and OR gates built from NANDs.

It’s also important to note that in problems requiring NAND-only circuits, the original circuit is typically presented in an AND-OR configuration—either standard or non-standard—which serves as the starting point for the conversion.

XNOR and Its NAND Equivalent Form

The IEEE symbol and truth table of an XNOR gate is given below. For a detailed understanding, please visit the XNOR gate page.

The XNOR gate, like the XOR gate, is not directly converted into its NAND equivalent form. Instead, its NAND-based implementation is derived from the original XNOR expression represented in either AND-OR or OR-AND form. For further clarity, refer to the XNOR gate’s implementation using Sum of Products (SOP) and Product of Sums (POS) forms on the relevant pages. These canonical forms serve as the foundation for converting the logic into NAND-only circuits using standard transformations for AND and OR gates built from NANDs.

It’s also important to note that in problems requiring NAND-only circuits, the original circuit is typically presented in an AND-OR configuration—either standard or non-standard—which serves as the starting point for the conversion.