A Complete Guide to Multiplexers: MUX Logic & Design

What is a Multiplexer?

A multiplexer (MUX) is a combinational logic device that selects one input from a set of \(\mathsf{2^n}\) data inputs and forwards it to a single output line. It uses an additional set of \(\mathsf{n}\) control inputs, known as select lines, to determine which of the \(\mathsf{2^n}\) inputs is routed to the output. Multiplexers are opposite of Demultiplexers.

Real-World Analogy

Think of a video projector that can receive signals from multiple sources—HDMI, VGA, or S-video. Although all sources are connected, the projector displays content from only one source at a time, based on the user’s selection. This mirrors how a MUX chooses one input to pass through, depending on the select line configuration.

Symbolic Representation of a Multiplexer

A multiplexer (MUX) is commonly depicted using a vertical trapezoid, where:

• The longer vertical edge connects to the \(\mathsf{2^n}\) data inputs.
• The shorter vertical edge represents the single output.
• The angled bottom edge typically receives the n select lines that determine which input is routed to the output.
• Inside the longer edge, the binary (or sometime decimal) values of the select lines corresponding to the input labels are typically shown.

However, alternative representations exist:

• Some diagrams use a vertical rectangle instead of a trapezoid.
• In certain texts, the select lines may be shown entering from the top edge, depending on stylistic or layout preferences.

Signal Width and Bus Notation

MUX inputs can be:

• Single-bit signals, where each input carries one binary value.
• Multi-bit signals of uniform width, such as 4-bit or 8-bit buses.

In multi-bit configurations:

• The output will also be a multi-bit signal of the same width.
• These buses are typically illustrated using:
  • Thicker lines to denote grouped wires and accompanied by a width annotation (e.g., [n:0]).
  • A slash or angled tick mark across the line (often called a bus slash or wire bundle indicator), accompanied by a number indicating the bit width.

Labeling and Select Line Representation

• The center of the MUX symbol may be labeled as \(\mathsf{2^n\times{}1}\) or \(\mathsf{2^n-to-1}\), which conveys:
  • The number of inputs.
  • The presence of n select lines, since 2n2^n inputs require nn bits to uniquely select one.
• Select lines can be shown:
  • As individual wires, each labeled separately.
  • Or as a bus, with a width annotation (e.g., [n:0]) to indicate the number of control bits.

Example Scope

This symbolic framework applies across various MUX configurations, such as:

• Single-bit 2-to-1 MUX
• 4-bit 2-to-1 MUX
• Single-bit 4-to-1 MUX
• 4-bit 4-to-1 MUX

These examples demonstrate how both data width and input count influence the visual and functional design of the MUX symbol.

Truth Table of a Multiplexer

The truth table of a multiplexer (MUX) can be conceptually simplified by recognizing its core behavior. A MUX has two distinct sets of inputs: the data inputs and the select lines. As the number of select lines increases, the number of data inputs grows exponentially—specifically, \(\mathsf{2^n}\) inputs for \(\mathsf{n}\) select lines. This exponential growth makes it impractical to represent every possible input combination explicitly in a full truth table, especially when each data input carries a unique signal. However, by focusing on the MUX’s selection mechanism, we can construct a concise truth table that captures its functionality without listing all input values. In this simplified form, only the select line combinations are shown in the input columns, and the output column indicates which input signal is routed to the output for each select configuration. This approach effectively conveys the MUX’s behavior and is commonly used to represent configurations like 2-to-1 and 4-to-1 multiplexers, as illustrated in accompanying figures.

In a standard 4-to-1 multiplexer configuration, the inputs are typically mapped in ascending binary order: input A is selected when the select lines represent binary 00 (decimal 0), B for 01 (1), C for 10 (2), and D for 11 (3). This default mapping ensures predictable routing based on the binary value of the select lines. However, this arrangement is not fixed—designers have the flexibility to assign any input to any select line combination, allowing for custom input-to-output mappings tailored to specific logic or application requirements.

Internal Circuit of a Multiplexer

We can solve for the logic diagram using the truth tables or K-maps. The internal architecture of a multiplexer (MUX) is typically built using a Sum of Products (SOP) logic configuration, involving layers of AND and OR gates. At the first level, there are \(\mathsf{2^n}\) AND gates—each corresponding to one possible combination of the \(\mathsf{n}\) select lines. Every AND gate has \(\mathsf{n+1}\) inputs: \(\mathsf{n}\) inputs for the select line minterm (ensuring only one gate activates for a given selection) and one input for the associated data signal. The outputs of all these AND gates are then fed into a single OR gate, which consolidates the signals and ensures that only the selected input is passed through to the final output. A single-bit 2-to-1 MUX’s internal logic diagram which outputs \(\mathsf{A}\) when \(\mathsf{S=0}\) and \(\mathsf{B}\) when \(\mathsf{S=1}\) is shown:

For multi-bit multiplexers, this logic structure is replicated in parallel for each bit of the input and output signals. That means if the data inputs are 4-bit wide, the entire AND-OR configuration is duplicated four times—once for each bit position. This parallelism allows the MUX to handle vectorized data while maintaining the same selection logic across all bits, as illustrated in the referenced figure.

Expanding MUX Inputs

Building a 4-to-1 MUX using 2-to-1 MUXes

Larger multiplexers can be constructed by cascading smaller ones—most commonly, 2-to-1 MUXes. For instance, a 4-to-1 MUX can be built using three 2-to-1 MUXes: two in the first layer to handle the four inputs in pairs, and one in the second layer to select between the outputs of the first two. Similarly, an 8-to-1 MUX would require seven 2-to-1 MUXes arranged in three layers: four in the first layer, two in the second, and one final MUX at the top. The general strategy involves grouping inputs in pairs, routing each pair through a 2-to-1 MUX, and then recursively combining their outputs in higher layers until a single output remains.

In this layered structure, select lines are assigned based on significance. The least significant bit (LSB) of the select lines controls the first layer of MUXes, toggling between adjacent input pairs. The next higher bit controls the second layer, and so on, with the most significant bit (MSB) reaching the final stage. This hierarchical design ensures that each layer refines the selection based on increasing bit significance. A 4-to-1 MUX built using this method demonstrates how modular logic can scale efficiently while maintaining predictable control flow.

Implementing Logic Functions Using a Multiplexer

Just as logic functions can be implemented using a decoder, they can also be realized using a multiplexer (MUX)—often with greater flexibility. When a function is defined or expressed through its truth table, it can be mapped directly onto a MUX by following a systematic approach:

Example : Implement the given function with the help of a MUX.

We shall work out the solution showing them visually step-by-step.

Step 1

Two rows are grouped together, starting from the top of the truth table.

Step 2

The input column with the LSB (C) is isolated. Remaining inputs are 2, A and B, that form the two select lines. Hence, we need a 4-to-1 MUX. A becomes the MSB select line \(\mathsf{S_1}\) while B becomes the LSB select line \(\mathsf{S_0}\).

Step 3

In each groups of 2 rows, output signal Z is compared with the LSB input C, to form the equality relation.

Step 4

MUX inputs are written in the order as the equality relations were created in last step.

Step 5

MUX’s output becomes the output logical function that we needed to implement using MUX.