A Complete Guide to Encoders: Priority, Symbols & Logic

What is an Encoder?

An encoder is a combinational logic circuit that performs the inverse function of a decoder. It takes \(\mathsf{2^n}\) input lines, where only one input is active (logic high) at any given timeโ€”this is known as the one-hot formatโ€”and converts that active input into an n-bit binary code representing its position.

Clarifications

  • “One-hot” means exactly one of the \(\mathsf{2^n}\) inputs is set to 1, while all others are 0.
  • The encoder outputs the binary index of the active input line.
  • For example, in a 4-to-2 encoder, if the third input line (corresponding to the index 2) is high, the output will be binary 10.
  • An Encoder has:
    • \(\mathsf{2^n}\) inputs presented as 0s except for 1 signal.
    • \(\mathsf{n}\) outputs: exhibiting the binary equivalent index value.

Symbolic Representation of an Encoder

An encoder is typically represented by a vertical rectangular symbol, with the input lines shown on the left side and the output lines on the right. An encoder symbol may be annotated asโ€ฏ\(\mathsf{2_n\times{}n}\)โ€ฏorโ€ฏ\(\mathsf{2^n-\textsf{to}-n}\)โ€ฏto denote its role in compressing \(\mathsf{2^n}\) one-hot inputs into their corresponding \(\mathsf{n}\)-bit binary representation.

this image shows the symbol of a 4-to-2 encoder
Symbol of a 4-to-2 Encoder

Truth Tables of an Encoder

Truth tables of \(\mathsf{4\times{}2}\) and \(\mathsf{8\times{}3,}\) are given here. It must be mentioned that only the allowed combinations are shown, otherwise 4-input function can have 16 unique combinations while those an 8-input function go as high as 256. The inputs and outputs are shown with MSB first (on the left-hand side). For clarity, the LSB has been marked with the index 0.

Truth Table of a \(\mathsf{4\times{}2}\) Encoder

this image shows the truth table (comprsing valid inputs only) of a 4-to-2 encoder

Complete Truth Table of a \(\mathsf{4\times{}2}\) Encoder

In this complete truth table, the entries in pink show the forbidden input combinations and that the output against those inputs is not valid.

this image shows the full truth table of a 4-to-2 encoder

Truth Table of a \(\mathsf{8\times{}3}\) Encoder

this image shows the truth table (comprsing valid inputs only) of a 8-to-3 encoder

Internal Circuit of a \(\mathsf{4\times{}2}\) Encoder

We can solve for the logic diagram using the truth tables or K-maps. However, with large number of inputs, it may become impractical to solve the k-map manually. A simpler workaround exists; from the truth table of an encoder, it’s evident that each unique one-hot input pattern corresponds to a distinct binary output. This means the encoder compresses positional information from \(\mathsf{2^n}\) inputs into an \(\mathsf{n}\)-bit binary code. Internally, the encoder uses OR gates to detect which input line is active and generate the corresponding binary representation. Each output bit is formed by logically combining specific input lines that contribute to that bit’s high state.

\[
\begin{align}
\mathsf{Z_0}&\mathsf{=A_1+A_3}\\
\mathsf{Z_1}&\mathsf{=A_2+A_3}
\end{align}
\]

this image shows the internal logic diagram of a 4-to-2 encoder
Internal Logic Diagram of a 4-to-2 Encoder

Problems with a Regular Encoder

A standard encoder assumes that its inputs are in one-hot format, meaning exactly one of the \(\mathsf{2^n}\) inputs is active (logic high) at any given time. If this condition is violatedโ€”such as when multiple inputs are high simultaneouslyโ€”the encoder may produce an incorrect or undefined binary output that does not correspond to the intended input index. To ensure reliable operation, the encoder must be constrained to receive strictly one-hot input patterns.

Why Priority Encoders Are Needed?

When multiple inputs may be active at once (i.e., the input is not guaranteed to be one-hot), a regular encoder fails to resolve ambiguity. This is where priority encoders come in:

  • Priority Resolution: They assign precedence to higher-order inputs. If multiple inputs are high, the one with the highest priority (usually the highest index) determines the output.
  • Additional Logic: Priority encoders include extra circuitry to detect and resolve conflicts, ensuring a deterministic output even under invalid input conditions.
  • Valid Output Flag: Many priority encoders also include a “valid” output signal to indicate whether any input is active at all, which helps downstream logic avoid misinterpretation.

Symbolic Representation of a Priority Encoder

A priority encoder is an encoder, and hence, displayed in the same way. A Valid (V) signal, may be added to the outputs, if present.

this image shows the symbol of a 4-to-2 priority encoder with valid ((v) output signal
Symbol of a 4-to-2 Priority Encoder with Valid (V) Output Signal

Truth Tables of a Priority Encoder

Truth tables of \(\mathsf{4\times{}2}\) and \(\mathsf{8\times{}3,}\) priority encoders are given here. All combinations are shown by means of using \(\mathsf{X}\), don’t care, to encode priority. The inputs and outputs are shown with MSB first (on the left-hand side). For clarity, the LSB has been marked with the index 0. The Valid (\(\mathsf{V}\)) output is invalid (0) when all inputs are 0, and 1 otherwise.

Truth Table of a \(\mathsf{4\times{}2}\) Priority Encoder

The placement of X, don’t care, values in the table show that in this configuration, \(\mathsf{A_3}\) has the highest priority as if it is detected as 1, all the other input signals are ignored and the corresponding output is produced.

this image shows the complete truth table (comprsing valid inputs only) of a 4-to-2 priority encoder with valid (v) output signal

Truth Table of a \(\mathsf{8\times{}3}\) Priority Encoder

The placement of X, don’t care, values in the table show that in this configuration, \(\mathsf{A_7}\) has the highest priority as if it is detected as 1, all the other input signals are ignored and the corresponding output is produced.

this image shows the complete truth table (comprsing valid inputs only) of a 8-to-3 priority encoder with valid (v) output signal

Internal Circuit of a \(\mathsf{4\times{}2}\) Priority Encoder

Solving Output Functions \(\mathsf{Z_0,Z_1,}\) and \(\mathsf{V}\) Using a Condensed Truth Table

We aim to derive the output expressions for \(\mathsf{Z_0,Z_1,}\) and \(\mathsf{V}\) by analyzing the corresponding Karnaugh maps (K-maps), populated directly from a condensed truth table. Although the truth table is logically complete, it does not list all 16 rows explicitly for the 4-input combinations. Instead, it uses wildcards (X) to represent multiple input combinations compactly.

this image shows the complete truth table (comprsing valid inputs only) of a 4-to-2 priority encoder with valid (v) output signal

Interpreting the Condensed Truth Table

  • Rows 1 & 2 represent the binary combinations 0000 (\(\mathsf{m_0}\)) and 0001 (\(\mathsf{m_1}\)).
  • Row 3 contains an X in \(\mathsf{A_0}\), denoting two combinations: 0010 (\(\mathsf{m_2}\)) and 0011 (\(\mathsf{m_3}\)). These are highlighted in pink in both the truth table and K-map.
  • Row 4 shows 01XX, representing four combinations: 0100 to 0111 (\(\mathsf{m_4}\) to \(\mathsf{m_7}\)), marked in blue.
  • Row 5 uses 1XXX, covering eight combinations: 1000 to 1111 (\(\mathsf{m_8}\) to \(\mathsf{m_{15}}\)), shown in green.

Deriving Output \(\mathsf{Z_1}\)

this image shows the k-map solution for the z1 output of the 4-to-2 priority encoder
  • Two prime implicants are identified:
    • \(\mathsf{A_3}\): Covers \(\mathsf{m_8}\) to \(\mathsf{m_{15}}\).
    • \(\mathsf{A_2}\): Covers \(\mathsf{m_4}\) to \(\mathsf{m_7}\) and \(\mathsf{m_{12}}\) to \(\mathsf{m_{15}}\).
  • The donโ€™t-care condition at mโ‚€ is treated as 0 to simplify the expression.

Final Expression:

\[\mathsf{Z_1=A_2+A_3}\]

Deriving Output \(\mathsf{Z_0}\)

this image shows the k-map solution for the z0 output of the 4-to-2 priority encoder
  • Again, two prime implicants emerge:
    • \(\mathsf{A_3}\): Covers \(\mathsf{m_0}\) to \(\mathsf{m_{15}}\).
    • \(\mathsf{A_1A_2′}\): Covers \(\mathsf{m_2,m_3,m_{10},m_{11}}\).
  • The donโ€™t-care at mโ‚€ is treated as 0 for minimal form.

Final Expression:

\[\mathsf{Z_0=A_3+A_1A_2′}\]

Deriving Output V (Valid Output Indicator)

this image shows the k-map solution for the v output of the 4-to-2 priority encoder
  • The V output is essentially the logical OR of all inputs.
  • Using the K-map, we identify four prime implicants, each grouping eight minterms:
    • \(\mathsf{A_3}\): Covers \(\mathsf{m_{8}}\) to \(\mathsf{m_{15}}\)
    • \(\mathsf{A_2}\): Covers \(\mathsf{m_4}\) to \(\mathsf{m_7}\) and \(\mathsf{m_{12}}\) to \(\mathsf{m_{15}}\)
    • \(\mathsf{A_1}\): Covers \(\mathsf{m_2,m_3,m_6,m_7,m_{10},m_{11},m_{14},m_{14}}\)
    • \(\mathsf{A_0}\): Covers \(\mathsf{m_1,m_3,m_5,m_7,m_9,m_{11},m_{13},m_{15}}\)

Final Expression:

\[\mathsf{V=A_3+A_2+A_1+A_0}\]

Final Internal Circuit of \(\mathsf{4\times{}2}\) Priority Encoder

this image shows the internal logic diagram of the 4-to-2 priority encoder with valid (v) output
Internal Logic Diagram of the 4-to-2 Priority Encoder with Valid (V) Output