A Complete Guide to Demultiplexers: DMUX Logic & Design

What is a Demultiplexer (DMUX)?

A demultiplexer (DMUX) combinational circuit actively performs the reverse function of a multiplexer (MUX) and closely resembles a decoder. It receives one input signal along with \(\mathsf{n}\) select lines, producing \(\mathsf{2^n}\) output signals. Based on the binary value encoded on the select lines, it connects only one output line to transmit the input signal.

Real World Usage

Two key practical uses of a demultiplexer (DMUX) are:

• Data Routing in Communication Systems: A DMUX directs a single input data stream to one of multiple output channels based on select lines, enabling efficient data distribution in applications like telecommunications or network switches.
• Memory Address Decoding: In digital systems, a DMUX selects specific memory locations or peripheral devices by decoding address signals, ensuring the input signal reaches the correct destination in microprocessors or memory management systems.

Symbolic Representation of a Demultiplexer

A demultiplexer (DMUX) is commonly represented using a vertical trapezoid, where:

• The shorter vertical edge connects to the single input signal.
• The longer vertical edge connects to the (\(\mathsf{2^n}\)) output lines.
• The angled bottom edge typically receives the (\(\mathsf{n}\)) select lines that determine which output line receives the input signal.
• Inside the longer edge, the binary (or sometimes decimal) values of the select lines corresponding to the output labels are typically shown.

However, alternative representations exist:

• Some diagrams use a vertical rectangle instead of a trapezoid.
• In certain texts, the select lines may enter from the top edge, depending on stylistic or layout preferences.

Signal Width and Bus Notation

DMUX inputs and outputs can be:

• Single-bit signals, where the input and each output carry one binary value.
• Multi-bit signals of uniform width, such as 4-bit or 8-bit buses.

In multi-bit configurations:

• The input is a multi-bit signal, and the selected output will also be a multi-bit signal of the same width.
• These buses are typically illustrated using:
  • Thicker lines to denote grouped wires, accompanied by a width annotation (e.g., [n:0]).
  • A slash or angled tick mark across the line (often called a bus slash or wire bundle indicator), accompanied by a number indicating the bit width.

Labeling and Select Line Representation

• The center of the DMUX symbol may be labeled as \(\mathsf{1\times{}2^n}\) or \(\mathsf{1-to-2^n}\), which conveys:
  • The single input.
  • The presence of (\(\mathsf{n}\)) select lines, since (\(\mathsf{2^n}\)) outputs require (\(\mathsf{n}\)) bits to uniquely select one.
• Select lines can be shown:
  • As individual wires, each labeled separately.
  • Or as a bus, with a width annotation (e.g., [n:0]) to indicate the number of control bits.

Example Scope

This symbolic framework applies across various DMUX configurations, such as:

• Single-bit 1-to-2 DMUX
• 2-bit 1-to-2 DMUX
• Single-bit 1-to-4 DMUX
• 2-bit 1-to-4 DMUX

These examples demonstrate how both data width and output count influence the visual and functional design of the DMUX symbol.

Truth Table of a Demultiplexer

A demultiplexer (DMUX) actively processes one main input signal alongside \(\mathsf{n}\) select lines, resulting in a total of \(\mathsf{n+1}\) inputs. It generates \(\mathsf{2^n}\) output signals. To streamline the truth table, we omit the main input signal and represent it symbolically in the outputs. Consequently, this approach produces condensed truth tables that fully capture the DMUX behavior while reducing complexity. Specifically, it eliminates one column by excluding the input signal and halves the number of rows by focusing solely on select line combinations. Moreover, these savings become more significant for multi-bit input and output signals, as the table structure scales efficiently. For example, a \(\mathsf{1\times{}2}\) DMUX truth table lists one select line and two outputs, showing the input routed to one output based on the select line value. Similarly, a \(\mathsf{1\times{}4}\) DMUX truth table uses two select lines to direct the input to one of four outputs, maintaining clarity with fewer entries.

Truth Table of a \(\mathsf{1\times{}2}\) Demultiplexer

Truth Table of a \(\mathsf{1\times{}4}\) Demultiplexer

Truth Table of a \(\mathsf{1\times{}8}\) Demultiplexer

Internal Circuit of a Demultiplexer

We can derive the logic diagram for a demultiplexer (DMUX) using its truth table or Karnaugh maps. The truth table reveals that each output activates for exactly one unique combination of select line values, indicating that every output corresponds to a distinct minterm of the select variables. Internally, the DMUX employs AND gates to generate these minterms, with each gate configured to detect a specific select input pattern. Additionally, all AND gates receive the main input signal, denoted as \(\mathsf{A}\). When the select lines enable a specific AND gate, the input signal \(\mathsf{A}\) passes through to the corresponding output: if \(\mathsf{A = 0}\), the output is 0, and if (\mathsf{A = 1}\), the output is 1. Meanwhile, all non-selected outputs remain at 0. This implementation mirrors that of a decoder with an enable signal. However, in a decoder, the input signals are termed select lines in a DMUX, and the enable signal in the decoder serves as the main input line in the DMUX.