A Complete Guide to Decoders: Logic, Symbols & Cascading

What is a Decoder?

A decoder circuit is a combinational logic device designed to interpret encoded input signals. It accepts \(\mathsf{n}\) binary input bits, which together represent a number in binary form. Since \(\mathsf{n}\) bits can represent \(\mathsf{2^n}\) distinct combinations, the decoder produces \(\mathsf{2^n}\) output lines. For any given input combination, the decoder activates exactly one output line—corresponding to the binary value of the input—while keeping all other outputs low. This output mechanism is called One-Hot State Coding and this selective activation makes decoders essential for tasks like address selection, data routing, and control logic. They are the opposite of encoders.

Enable Input

In many decoder circuits, an Enable (En) input is included to control whether the decoder is active. As the name suggests, the Enable signal determines whether the device performs its intended decoding function or remains inactive. When the decoder is enabled, it responds to the input signals and activates the corresponding output line. When disabled, all outputs remain inactive—typically held low.

The Enable signal can be configured as either active-high or active-low, depending on the design:

• Active-high: The decoder is enabled when En = 1.
• Active-low: The decoder is enabled when En = 0.

This flexibility allows designers to integrate decoders into larger systems with conditional control, improving modularity and power efficiency.

Symbolic Representation of a Decoder

A decoder is typically represented by a vertical rectangular symbol, with the input lines shown on the left side and the output lines on the right. The center of a decoder symbol is often labeled as \(\mathsf{n\times{}2^n}\) or \(\mathsf{n-\textsf{to}-2^n}\) to clearly indicate its function: converting an \(\mathsf{n}\)-bit binary input into one of \(\mathsf{2^n}\) distinct output lines, typically in one-hot format.

If the decoder includes an Enable (En) signal, it is usually connected at the top or bottom edge of the symbol.

• When the Enable is active-high, it appears as a direct connection.
• When the Enable is active-low, a bubble (inversion circle) is placed at the connection point to indicate that the decoder is enabled when the signal is low.

This symbolic convention helps clearly convey the decoder’s activation logic and is widely used in schematic diagrams and digital design documentation. These different forms of a \(\mathsf{2\times{}4}\) decoder are shown here.

Truth Tables of a Decoder

Truth tables of \(\mathsf{2\times{}4}\) and \(\mathsf{3\times{}8,}\) with (active-high and active-low) Enable and without Enable are given below:

Truth Tables of a \(\mathsf{2\times{}4}\) Decoder

Truth Table of a \(\mathsf{2\times{}4}\) Decoder Without Enable

Truth Tables of a \(\mathsf{2\times{}4}\) Decoder With Active-high Enable

Truth Tables of a \(\mathsf{2\times{}4}\) Decoder With Active-low Enable

Truth Tables of a \(\mathsf{3\times{}8}\) Decoder

Truth Table of a \(\mathsf{3\times{}8}\) Decoder Without Enable

Truth Tables of a \(\mathsf{3\times{}8}\) Decoder With Active-high Enable

When Enable is low, the normal working of the decoder is disabled and all outputs produce a logic low. Instead of showing all the combinations of A, B and C, explicitly, they are all condensed into one row with A = B = C = X, where X denotes a “don’t care” condition.

Truth Tables of a \(\mathsf{3\times{}8}\) Decoder With Active-low Enable

When the Enable signal is high, the decoder is effectively disabled, and all output lines remain at logic low regardless of the input values. In the truth table, rather than listing every possible combination of inputs (such as A, B, and C), this inactive state is typically represented by a single condensed row using A = B = C = X, where X denotes a “don’t care” condition. This notation indicates that the inputs are irrelevant when the decoder is not enabled, simplifying the representation of its behavior.

Internal Circuit of a Decoder

We can solve for the logic diagram using the truth tables or K-maps. From the truth table of a decoder, it’s evident that each output is high for exactly one unique combination of input values. This means that every output corresponds to a distinct minterm of the input variables. Internally, the decoder generates these minterms using AND gates, where each gate is configured to recognize one specific input pattern.

When an Enable (En) signal is present (this is similar to the internal circuit of a demultiplexer):

• For an active-high Enable, the En signal is included as an additional input to each AND gate. The gate produces a high output only when both the input pattern and En are high.
• For an active-low Enable, the complement of En is fed into the AND gates, ensuring that outputs are active only when En is low.

This structure ensures that the decoder only responds when enabled, and that each output line uniquely represents one minterm of the input space. The internal circuit diagram of a \(\mathsf{2\times{}4}\) decoder without enable, with active-high enable and active-low enable is shown.

Expanding Decoder Inputs Through Cascading Logic

Larger decoders can be constructed by cascading smaller decoders that include an Enable input, allowing you to expand the input space modularly. In such configurations, one or more of the higher-order input bits are used to control the Enable signals of the smaller decoders. This ensures that only one decoder is active at a time, while the others remain disabled, preventing multiple outputs from being asserted simultaneously. The Enable input effectively acts as an additional control line, allowing the combined structure to behave like a single, larger decoder. This hierarchical approach supports scalable design and simplifies implementation in complex digital systems.

Building a \(\mathsf{3\times{}8}\) Decoder from two \(\mathsf{2\times{}4}\) Decoders with Active-high Enable

A \(\mathsf{3\times{}8}\) decoder (without a dedicated Enable) can be constructed using two \(\mathsf{2\times{}4}\) decoders, each equipped with an Enable (En) signal. In this setup, the En signal is active-high, and serves as a control signal that determines which of the two \(\mathsf{2\times{}4}\) decoders is enabled at any given time. This En signal becomes the third input of the \(\mathsf{3\times{}8}\) decoder. Now, depending on the user choice, it may be connected as the MSB, LSB or even index 1 bit.

When En is Connected as the MSB

• When the MSB is 0, the first decoder is enabled and handles input combinations 000 to 011.
• When the MSB is 1, the second decoder is enabled and handles combinations 100 to 111.

When En is Connected as the LSB

• When the LSB is 0, the first decoder is enabled and handles input combinations 000, 010, 100 and 110.
• When the LSB is 1, the second decoder is enabled and handles combinations 001, 011, 101 and 111.

Implementing a Function Through Decoder

Implementing a function using a decoder is a highly intuitive process. Since a decoder inherently generates all possible minterms for a given set of input variables, constructing a function in Sum of Products (SOP) form becomes a matter of selecting the required minterms—those that correspond to the function’s truth table—and combining them using an OR gate. This approach leverages the decoder’s built-in ability to produce one-hot outputs, making it ideal for modular and systematic logic design. We can also implement a given function using Multiplexers which is discussed on the relevant page.

Example 1: Implement the Output Function \(\mathsf{Z=\sum}\)\(\mathsf{\left(0,5\right)}\)

To implement this we simply pull the minterms \(\mathsf{m_0}\) and \(\mathsf{m_5}\) and attach it as an input to the OR gate to produce the final output Z.

Example 2: Implement the Output Function \(\mathsf{Z=\sum}\)\(\mathsf{\left(1,3,5\right)}\)

To implement this we simply pull the minterms \(\mathsf{m_1, m_3}\) and \(\mathsf{m_5}\) and attach it as an input to the OR gate to produce the final output Z.