What is a Ripple Carry Adder?
A ripple carry adder is a combinational logic circuit used to perform binary addition across multiple bits. It consists of a series of full adders connected in cascade, where each adder computes the sum of corresponding input bits along with a carry-in. The carry-out from each stage “ripples” forward as the carry-in to the next stage. As a result, the final sum and carry-out are only valid after all preceding carry signals have propagated through the chain—introducing a delay proportional to the number of bits.
Ripple Carry Addition: Step-by-Step Visual Explanation
We’re adding two 4-bit binary numbers:
- \(\require{boldsymbol}\boldsymbol{\mathsf{A=1010_2}}\)
- \(\boldsymbol{\mathsf{B=1011_2}}\)
- Initial Carry-in (\(\boldsymbol{\mathsf{C_0=0_2}}\))
Although all bits of \(\mathsf{A}\) and \(\mathsf{B}\) are available simultaneously and each pair enters its respective full adder, the validity of outputs depends on the propagation of carry bits. Here’s how the process unfolds:
Step 1: Index 0 (Least Significant Bit)
- Inputs: \(\mathsf{A_0=0,B_0=1,C_0=0}\).
- The full adder computes the Sum and Carry-out.
- Sum (\(\mathsf{S_0=1}\)) and Carry-out (\(\mathsf{C_1=0}\)) become valid at the end of this step.
- All other outputs remain invalid because they depend on \(\mathsf{C_1}\).
Step 2: Index 1
- Inputs: \(\mathsf{A_1=1,B_1=1,C_1=0\textsf{ (from previous step)}}\).
- Once \(\mathsf{C_1}\) arrives, the full adder at index 1 produces a valid Sum and Carry-out.
- Sum (\(\mathsf{S_1=0}\)) and Carry-out (\(\mathsf{C_2=1}\)) become valid at the end of this step.
- Outputs at index 2 and 3 are still invalid.
Step 3: Index 2
- IInputs: \(\mathsf{A_2=0,B_2=0,C_2=1\textsf{ (from previous step)}}\).
- The third full adder now computes Sum and Carry-out.
- Sum (\(\mathsf{S_2=1}\)) and Carry-out (\(\mathsf{C_3=0}\)) become valid at the end of this step.
- Outputs at index 3 are still invalid.
Step 4: Index 3 (Most Significant Bit)
- Inputs: \(\mathsf{A_3=1,B_3=1,C_3=0\textsf{ (from previous step)}}\).
- The final full adder produces Sum and the final Carry-out.
- Sum (\(\mathsf{S_3=0}\)) and Carry-out (\(\mathsf{C_4=1}\)) become valid at the end of this step.
- At the end of this step, all sum bits and the final carry-out are valid. \(\mathsf{C_4}\) becomes the valid \(\mathsf{C_o}\) of the complete 4-bit addition.
Final Output
- Sum = 0101
- Carry-out = 1
This stepwise validation illustrates why ripple carry adders introduce delay: each stage must wait for the previous carry to propagate before producing a valid result.
Hardware Implementation of a 4-Bit Ripple Carry Adder
The circuit layout mirrors the stepwise logic of ripple carry addition. Each of the four full adders (labeled as \(\mathsf{FA1-FA4}\)) corresponds to one bit position, connected in sequence:
- The initial carry-in (\(\mathsf{C_0=C_i}\)) feeds directly into the Carry-in of the first full adder (index 0).
- The Carry-out from each adder becomes the Carry-in for the next, forming a ripple chain.
- This continues through all four stages.
- The Carry-out from the final full adder serves as the final Carry-out (\(\mathsf{C_4=C_o}\)) of the entire 4-bit addition.
This cascading structure ensures that each stage waits for the previous carry to resolve before producing a valid output—just as illustrated in the visual walkthrough.
Verilog Code of a 4-bit Ripple Carry Adder Circuit
Verilog HDL module of a half adder is instantiated in the full adder module which is further invoked here 4 times to implement a 4-bit ripple carry adder.
module ripple_adder_4(
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire C1,C2,C3;
full_adder FA1(
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(C1)
);
full_adder FA2(
.A (A[1]),
.B (B[1]),
.Ci(C1),
.S (S[1]),
.Co(C2)
);
full_adder FA3(
.A (A[2]),
.B (B[2]),
.Ci(C2),
.S (S[2]),
.Co(C3)
);
full_adder FA4(
.A (A[3]),
.B (B[3]),
.Ci(C3),
.S (S[3]),
.Co(Co)
);
endmodule
Latency of a 4-Bit Ripple Carry Adder
Before we calculate the latency of the circuit, let’s assume the following delay values for all the standard logic gates.
\[
\begin{align}
\textsf{NOT: }&\mathsf{10\,ps}\\
\textsf{NAND/NOR: }&\mathsf{20\,ps}\\
\textsf{AND/OR: }&\mathsf{30\,ps}\\
\textsf{XOR: }&\mathsf{40\,ps}\\
\textsf{XNOR: }&\mathsf{50\,ps}
\end{align}
\]
At first glance, the gate propagation delay values may seem unclear, especially since the ripple carry adder schematic doesn’t explicitly show individual logic gates. However, it’s important to recognize that each full adder in the ripple carry chain is internally constructed using two half adders and an OR gate. The delay values provided correspond to the gate-level latency of this internal structure.
Each full adder introduces a delay of 100 ps, based on the given data and cumulative latency of its constituent gates. Since the ripple carry adder operates sequentially—where each full adder waits for the carry-out from the previous stage—the delays accumulate linearly. For a 4-bit ripple carry adder, this results in a total propagation delay of:
- 4 full adders × 100 ps = 400 ps
This sequential nature is what gives the ripple carry adder its name—and its latency.
Extending the Ripple Carry Adder to Higher Bit Widths
Scaling a ripple carry adder to handle more bits is straightforward: we simply extend the number of full adders. This can be done in two ways:
- Manual Expansion: Add 16 individual full adders in sequence, just as we did for the 4-bit version.
- Modular Composition: Reuse the 4-bit ripple carry adder as a building block. By chaining four of these blocks together, we construct a 16-bit ripple carry adder. This modular 16-bit unit can then be replicated four times to build a 64-bit ripple carry adder with ease.
The figure shown illustrates how a 16-bit adder is assembled using four 4-bit ripple carry adder blocks, each connected via carry-out to carry-in, maintaining the ripple structure across blocks.
Verilog Code of a 16-bit Ripple Carry Adder Circuit
Verilog HDL module of 4-bit ripple-carry adder is used instantiated here to implement a 16-bit ripple-carry adder.
module ripple_adder_16(
input [15:0] A,
input [15:0] B,
input Ci,
output [15:0] S,
output Co
);
wire C1,C2,C3;
ripple_adder_4 RCA1(
.A (A[3:0]),
.B (B[3:0]),
.Ci(Ci),
.S (S[3:0]),
.Co(C1)
);
ripple_adder_4 RCA2(
.A (A[7:4]),
.B (B[7:4]),
.Ci(C1),
.S (S[7:4]),
.Co(C2)
);
ripple_adder_4 RCA3(
.A (A[11:8]),
.B (B[11:8]),
.Ci(C2),
.S (S[11:8]),
.Co(C3)
);
ripple_adder_4 RCA4(
.A (A[15:12]),
.B (B[15:12]),
.Ci(C3),
.S (S[15:12]),
.Co(Co)
);
endmodule