A Complete Guide to a Half Adder: Definition, Design and Latency

What is a Half Adder?

A half adder is the foundational unit of a ripple carry adder. It takes two binary inputs and produces two outputs: the sum bit and the carry-out bit.

Why is it Called a Half Adder?

A half adder is called “half” because it performs only part of the full binary addition process. While it might seem like we’re simply adding two digits, binary addition typically involves three inputs: the two bits being added and a carry-in from the previous stage. In isolated cases, the carry-in is often zero, which makes it easy to overlook. However, in multi-bit addition—like in ripple carry adders—each bit addition includes a carry-in. Since the half adder doesn’t account for this third input, it handles only the sum and carry-out of two bits, not the full three-input logic. That’s why it’s considered “half” of a full adder.

Designing a Half Adder

In this section, we’ll build a half adder combinational logic device from the ground up. We’ll start by constructing its truth table, then simplify the output expressions for the sum and carry bits using Karnaugh maps. Once we’ve derived the minimal logic functions, we’ll draw the corresponding circuit diagram. Finally, we’ll analyze the circuit to determine its latency.

Truth Table of a Half Adder

To begin designing a half adder, we first consider all possible input combinations for its two variables, labeled \(\mathsf{A}\) and \(\mathsf{B}\). Each pair of inputs produces a two-bit result: the Sum (\(\mathsf{S}\)), highlighted in pink, and the Carry-out (\(\mathsf{C_o}\)), shown in blue.

By evaluating the outputs for every input case, we compile a complete set of input-output relationships. This data is then organized into a truth table, which serves as the standard starting point for analyzing and implementing any digital logic function. The corresponding truth table is displayed in the image below.

Output Functions of a Half Adder

With the truth table in place, we now simplify both output functions using Karnaugh maps—starting with the Sum ((\mathsf{S})). In the K-map for (\mathsf{S}), no adjacent grouping of two cells is possible, so the minimal expression remains in Sum of Products (SOP) form. Interestingly, this SOP structure directly mirrors the behavior of an XOR gate, as confirmed by comparing it to XOR’s truth table.

\[\mathsf{S=A’B+AB’=A\oplus{}B\oplus{}C_i}\]

Next, we analyze the Carry-out (\(\mathsf{C_o}\)) output using its K-map. The simplification is straightforward: the only active cell corresponds to the condition where both inputs are 1. This yields a clean Boolean expression—A AND B—matching the output of a standard AND gate.

\[\mathsf{C_o=AB}\]

Logic Diagram of a Half Adder

With the Boolean expressions for both outputs—Sum (S) and Carry-out (Co)—now derived, we can translate them into their corresponding logic circuit. Inputs \(\mathsf{A}\) and \(\mathsf{B}\) are fed into an XOR gate to generate the Sum (\(\mathsf{S}\)) output, while the same inputs pass through an AND gate to produce the Carry-out (\(\mathsf{C_o}\)) signal. This forms the complete gate-level diagram of the half adder.

Verilog Code of a Half Adder Circuit

Verilog HDL code for the half adder module is given below at gate, dataflow and behavioral level. All three codes are synthesizable and can be used as the base code for half adder block.

Gate Level Code

module half_adder(
    input A,
    input B,
    output S,
    output Co
    );
    xor x1(S,A,B);
    and a1(Co,A,B); 
endmodule

Dataflow Level Code

module half_adder(
    input A,
    input B,
    output S,
    output Co
    );
    assign S=A^B;
    assign Co=A&B; 
endmodule

Behavioral Level Code

module half_adder(
    input A,
    input B,
    output reg S,
    output reg Co
    );
    always @* begin
      S=A^B;
      Co=A&B;
    end 
endmodule

Latency of a Half Adder

Before we calculate the latency of the circuit, let’s assume the following delay values for all the standard logic gates.

\[
\begin{align}
\textsf{NOT: }&\mathsf{10\,ps}\\
\textsf{NAND/NOR: }&\mathsf{20\,ps}\\
\textsf{AND/OR: }&\mathsf{30\,ps}\\
\textsf{XOR: }&\mathsf{40\,ps}\\
\textsf{XNOR: }&\mathsf{50\,ps}
\end{align}
\]

The half adder circuit features two main signal paths from inputs to outputs: one passing through the XOR gate and the other through the AND gate. The XOR gate introduces a delay of 40 ps, while the AND gate contributes a 30 ps delay. Since the overall latency is determined by the slower path, the total propagation delay for this circuit—based on the provided data—is 40 ps.