A Complete Guide to a Full Adder: Definition, Design and Latency

What is a Full Adder?

A full adder extends the functionality of a half adder by accounting for an additional input—the carry-in from a previous stage. It takes three binary inputs: two operand bits (\(\require{boldsymbol}\mathsf{A}\) and \(\mathsf{B}\)) and a carry-in bit (\(\mathsf{C_i}\)), and produces two outputs: the Sum bit (\(\mathsf{S}\)) and the Carry-out (\(\mathsf{C_o}\)).

This makes it suitable for chained addition in multi-bit systems, where each bit position must consider the carry propagated from the lower-order bit. In essence, the full adder performs complete single-bit binary addition with carry handling, making it the core building block of ripple carry and carry lookahead adders.

Why is it Called a Full Adder?

A full adder is called “full” because it performs the complete binary addition required at each bit position in multi-bit arithmetic. Unlike a half adder, which only adds two bits, the full adder accounts for three inputs: the two operand bits (A and B) and the Carry-in (\(\mathsf{C_i}\)) from the previous stage. This third input is essential in chained addition, such as in ripple carry or carry lookahead adders, where each bit’s result depends not only on its own operands but also on the carry propagated from the lower-order bit. By handling all three inputs and producing both a Sum (S) and a Carry-out (\(\mathsf{C_o}\)), the full adder completes the logic that the half adder only begins—hence the name “full” adder.

Design a Full Adder

In this section, we’ll construct a full adder combinational logic device using two complementary approaches. First, we’ll build the full adder directly by analyzing its three-input truth table and simplifying the output expressions for the sum and carry bits using Karnaugh maps. This method gives us a clear view of the minimal logic required. Then, we’ll explore a modular design using two half adders and an OR gate—highlighting how smaller building blocks can be combined to achieve the same functionality. Once both designs are complete, we’ll compare their circuit diagrams and evaluate their respective latencies and gate complexities.

Design a Full Adder Independently

In this section, we’ll design the full adder directly from its truth table, without incorporating the half adder developed earlier.

Truth Table of a Full Adder Designed Independently

To construct the truth table for a full adder, we begin by defining the three input variables: \(\mathsf{A,B,}\) and the Carry-in (\(\mathsf{C_i}\)). Each row of the table represents a unique combination of these inputs. The corresponding output columns display the resulting Sum (\(\mathsf{S}\)) (shown in pink) and Carry-out (\(\mathsf{C_o}\)) (highlighted in blue) for each case. This tabular representation captures the complete behavior of the full adder across all possible input states.

Output Functions of a Full Adder Designed Independently

With the truth table established, we now simplify the Sum \(\mathsf{S}\) output using a Karnaugh map. Since the full adder has three inputs—\(\mathsf{A,B,}\) and Carry-in (\(\mathsf{C_i}\))—the K-map spans eight cells. Upon mapping the truth table values, we identify groupings that lead to a minimal Sum of Products (SOP) expression. Interestingly, the resulting logic mirrors a three-input XOR operation, as evident from the zigzag placement of 1s in the 3-input K-map which does not allow us to group any 1s together:

\[\mathsf{S=A’B’C_i+A’BC_i’+AB’C_i’+ABC_i=A\oplus{}B\oplus{}C_i}\]

This equivalence becomes clear when comparing the output pattern to the XOR truth table extended to three variables. The Sum bit is high when an odd number of inputs are high, which is the defining behavior of chained XOR gates.

Next, we simplify the Carry-out (\(\mathsf{C_o}\)) output of the full adder using its Karnaugh map. With three inputs—\(\mathsf{A,B,}\) and Carry-in (\(\mathsf{C_i}\))—the K-map spans eight cells. After plotting the output values, we identify groupings that lead to the minimal Boolean expression. We can identify three distinct pairs of adjacent 1s in the Karnaugh map: grouping \(\mathsf{m_6}\) and \(\mathsf{m_7}\) yields the term \(\mathsf{AB}\), \(\mathsf{m_5}\) and \(\mathsf{m_7}\) produce \(\mathsf{AC_i}\), and \(\mathsf{m_3}\) and \(\mathsf{m_7}\) result in \(\mathsf{BC_i}\). Each pair corresponds to a product term in the simplified Carry-out \(\mathsf{C_o}\) expression.:

\[\mathsf{C_o=AB+AC_i+BC_i}\]

This expression reflects the conditions under which a carry is generated: when any two or all three inputs are high. Unlike the half adder, where carry-out is simply A AND B, the full adder’s carry logic accounts for multiple carry-generating paths. The result is a more complex, yet optimized, Sum of Products form that can be implemented using AND and OR gates.

Logic Diagram of a Full Adder Designed Independently

With the Boolean expressions for both outputs—Sum \(\mathsf{S}\) and Carry-out \(\mathsf{C_o}\)—already established, we can now construct the corresponding logic circuit for the full adder. The inputs \(\mathsf{A,B,}\) and Carry-in \(\mathsf{C_i}\) are first processed through a pair of XOR gates: \(\mathsf{A}\) and \(\mathsf{B}\) feed into the first XOR gate, and its output is then combined with \(\mathsf{C_i}\) in the second XOR gate to produce the Sum \(\mathsf{S}\) output. In parallel, three AND gates evaluate the pairwise combinations of the inputs—\(\mathsf{AB, AC_i,}\) and \(\mathsf{BC_i}\)—and their outputs are merged through an OR gate to generate the final Carry-out \(\mathsf{C_o}\) signal. Together, these gates form the complete gate-level diagram of the full adder, extending the half adder’s logic to accommodate carry propagation across bit positions.

Verilog Code of a Full Adder Circuit

Verilog HDL code for the full adder module that is independently designed is given below at gate, dataflow and behavioral level. These codes are synthesizable and can be used as the base code for full adder block. Intermediate variables used in the code are not shown in the figure but intuitive in nature.

Gate Level Code

module full_adder(
    input A,
    input B,
    input Ci,
    output S,
    output Co
    );
    wire S1,C1,C2,C3;
    xor x1 (S1,A,B);
    xor x2 (S,S1,Ci);
    and a1 (C1,A,B);
    and a2 (C2,A,Ci);
    and a3 (C3,B,Ci);
    or  o1 (Co,C1,C2,C3);
endmodule

Dataflow Level Code

module full_adder(
    input A,
    input B,
    input Ci,
    output S,
    output Co
    );
    assign S=(A^B)^Ci;
    assign Co=(A&B)|(A&Ci)|(B&Ci);
endmodule

Behavioral Level Code

module full_adder(
    input A,
    input B,
    input Ci,
    output S,
    output Co
    );
    always @* begin
      S=(A^B)^Ci;
      Co=(A&B)|(A&Ci)|(B&Ci);
    end
endmodule

Latency of a Full Adder Designed Independently

Before we calculate the latency of the circuit, let’s assume the following delay values for all the standard logic gates.

\[
\begin{align}
\textsf{NOT: }&\mathsf{10\,ps}\\
\textsf{NAND/NOR: }&\mathsf{20\,ps}\\
\textsf{AND/OR: }&\mathsf{30\,ps}\\
\textsf{XOR: }&\mathsf{40\,ps}\\
\textsf{XNOR: }&\mathsf{50\,ps}
\end{align}
\]

The full adder circuit, when designed independently, features two primary signal paths from inputs to outputs: one for computing the Sum (\(\mathsf{S}\)) and the other for generating the Carry-out (\(\mathsf{C_o}\)). The Sum path involves two sequential XOR gates, each introducing a delay of 40 ps, resulting in a total delay of 80 ps for this output. Meanwhile, the Carry-out path consists of three parallel AND gates, each producing its output after 30 ps. These outputs are then combined through an OR gate, which adds another 30 ps of delay, bringing the total for this path to 60 ps. Since the overall latency is determined by the longest path, the total propagation delay for the full adder—based on this configuration—is 80 ps.

Designing a Full Adder Based on Half Adder

In this section, we’ll construct the full adder by leveraging the half adder circuit developed previously.

Truth Table of a Full Adder Based on Half Adder

The truth table of the full adder remains unchanged, even when its implementation is based on the half adder circuit. This is because the underlying functionality of the full adder is consistent regardless of the design approach.

Output Functions and Logic Diagram of a Full Adder Based on Half Adder

If we were to solve the full adder output functions purely from the truth table, we’d arrive at the same Boolean expressions as before—without any opportunity to reuse the half adder circuit we previously designed. To make the design more modular, we’ll instead combine the steps of function simplification and circuit construction in a way that incorporates the half adder.

Designing the Sum (\(\mathsf{S}\)) Output

We know that a half adder uses an XOR gate to compute the sum and an AND gate to produce the carry-out. When we simplify the full adder’s Sum output using a K-map we get:

\[\mathsf{S=A’B’C_i+A’BC_i’+AB’C_i’+ABC_i=A\oplus{}B\oplus{}C_i}\]

The result is a two-stage XOR operation: the first XOR takes inputs A and B, and the second XOR combines that result with the carry-in \(\mathsf{C_i}\). This structure aligns perfectly with two chained half adders. The first half adder processes A and B, and its Sum output becomes the input to a second half adder, which then takes \(\mathsf{C_i}\) as its second input. The final Sum output of the full adder is simply the Sum output of this second half adder. This approach allows us to build the full adder using modular, reusable logic blocks.

Designing the Carry-out (\(\mathsf{C_o}\)) Output

So far, we’ve used two half adders to compute the Sum (\(\mathsf{S}\)) output of the full adder. However, this setup inherently fixes the connections: inputs \(\mathsf{A}\) and \(\mathsf{B}\) are wired to the first half adder, while the output of its XOR gate—\(\mathsf{A\oplus{}B}\)—along with the Carry-in \(\boldsymbol{\mathsf{C_i}}\), are fed into the second half adder. As a result, the AND gate in the first half adder produces the term \(\mathsf{AB}\), and the AND gate in the second half adder yields \(\mathsf{\left(A\oplus{}B\right)C_i}\).

The term \(\mathsf{AB}\) is a prime implicant that covers the minterms \(\mathsf{m_6}\) and \(\mathsf{m_7}\).

Let’s now solve \(\mathsf{\left(A\oplus{}B\right)C_i}\) by converting \(\mathsf{A\oplus{}B}\) into its AND-OR equivalent form to find out exactly what implicants are covered by them.

\[
\begin{align}
\mathsf{\left(A\oplus{}B\right)C_i }&\mathsf{=\left(AB’+A’B\right)C_i}\\
&\mathsf{=AB’C_i+A’BC_i}\\
&\mathsf{=m_5+m_3}\\
&\mathsf{=\sum\left(3,5\right)}
\end{align}
\]

From this breakdown, we see that all four minterms contributing to the Full Adder’s Carry-out \(\mathsf{C_o}\) are accounted for by the outputs of the two half adder circuits. The first Half Adder’s Carry-out covers minterms \(\mathsf{m_6}\) and \(\mathsf{m_7}\), while the second covers \(\mathsf{m_3}\) and \(\mathsf{m_5}\). To obtain the complete \(\mathsf{C_o}\) function, we simply take the logical OR of these two carry outputs, as illustrated in the accompanying diagram.

The Final Schematic of a Full Adder Based on Half Adder

The final logic diagram of a full adder that is built using two half adders and an OR gate is shown:

Verilog Code of a Full Adder Circuit

Verilog HDL module of a half adder is instantiated here to implement a full adder.

module full_adder(
    input A,
    input B,
    input Ci,
    output S,
    output Co
    );
    wire S1,C1,C2;
    half_adder ha1(
        .A (A),
        .B (B),
        .S (S1),
        .Co(C1)
        );
    half_adder ha2(
        .A (S1),
        .B (Ci),
        .S (S),
        .So(C2)
        );    
    assign Co=C1|C2;
endmodule

Latency of a Full Adder Based on Half Adder

Before we calculate the latency of the circuit of this full adder built using half adders, let’s assume the following delay values for all the standard logic gates.

\[
\begin{align}
\textsf{NOT: }&\mathsf{10\,ps}\\
\textsf{NAND/NOR: }&\mathsf{20\,ps}\\
\textsf{AND/OR: }&\mathsf{30\,ps}\\
\textsf{XOR: }&\mathsf{40\,ps}\\
\textsf{XNOR: }&\mathsf{50\,ps}
\end{align}
\]

The full adder circuit, when designed independently, features two primary signal paths from inputs to outputs: one for computing the Sum (\(\mathsf{S}\)) and the other two for generating the Carry-out (\(\mathsf{C_o}\)).

The Sum path involves two sequential XOR gates, each introducing a delay of 40 ps, resulting in a total delay of 80 ps for this output. This path has been shown by the pink path line.

Meanwhile, the first Carry-out path consists of the AND gate of the first half adder and the OR gate, with both gates producing their output after 30 ps. These outputs produce a total delay of 60 ps and this path is shown in lavender, going through the first input of the OR gate, in the figure.

The second Carry-out path is through the AND gate of the second half adder and the final OR gate, which should again give a delay of 60 ps. However, the AND gate of the second half adder takes \(\mathsf{C_i}\) at its input, which is available from the start of the addition process, but its other input is waiting for a valid value from the XOR gate of the first half adder. Hence, there a further delay of 40 ps before this AND gate could produce a valid result. Thus, the delay of this path, which is shown in yellow, and going through the second input of the OR gate is 100 ps.

Since the overall latency is dictated by the longest signal path, the total propagation delay for the full adder—based on this modular configuration—is 100 ps. Although this design introduces slightly higher latency compared to the independently built version, it benefits from a modular structure that simplifies construction and promotes reuse. From a cost perspective, the modular approach proves more efficient, requiring fewer unique components and reducing overall gate complexity relative to a fully custom implementation.